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hi, everyone
in the field of asynchronous circuit, it says that there is an empty token in the 4-phase handshake protocol, but not in the 2-phase handshake protocol, i really want to know why. just because the level-triggered return-to-zero request and acknowledge handshake signals?
thanks in...
i know it can be observed from the amplitude and phase Bode plots of the open-loop gain or loop gain.
but can you tell me the exact equation(s) between phase margin and pole points?
plz help me, thanks in advance.
jeffrey
"the basic differential pair" VS " the differential pair with active current mirror"
can you tell me the differences between "the basic differential pair" and "the differential with active current mirror" ?
i know the latter increases a "mirror pole", i.e., it has worse stability.
what are...
hi, everyone
"For pull down time of a 4-input NAND gate, due to velocity saturation, the effective resistance of the four series NMOS will be reduced, so you will not see a 4Rn but less may be 2.5Rn to 3Rn. "
can u explain it clearly ?
plz
and
thanks
sevid
equal rise and fall time nand
hi, everyone
"2). For pull down time, due to velocity saturation, the effective resistance of the Four series NMOS will be reduced, so you will not see a 4Rn but less may be 2.5Rn to 3Rn. "
can u explain it clearly ?
plz
and
thanks
sevid
hi,everyone
my Q is how to get the max freqency of ur design from the synthesis results of DC ?
from the "data arrival time" ?
but i find that there are different "data arrival time"s when different clock cycles are set in ur tcl scripts, and all of these different clock cycles may meet the...
hi,everyone
"one of the inverters should be replaced with a NAND gate to turn the ring oscillator off when not in use."
i dont know how to turn it off just by a NAND gate.
how to connect the NAND to other inverters ?
plz help me.
thanks
sevid
hi, everyone
i am looking for the solutions of the book, modern vlsi design: system-on-chip design, 3rd edition.
who uploads it or gives an link will be very appreciated.
sevid
html + dependent pulldown
hi, tariq786, thanks a lot.
but for the first method, the input will be 0000 or 0111, and the efficient resistance is not equal obviously.
i.e., one, two, three, or four PMOSes of the pullup network will be on for various inputs.
does probability need to be taken...
pull up time
hi,everyone
how to make ur pullup time and pulldown time equal in ur gate, for example, a 4-input NAND gate.
if the efficient resistance of a NMOS in the pulldown network is Rn, the total resistance is 4Rn.
but what's the total resistance or average total resistance of the...
about spacings
hi
there is 3 questions here
1 why is ndiff-to-pdiff spacing so large?
2 why is metal-metal spacing larger than poly-poly spacing?
3 why is metal2-metal2 spacing larger than metal1-metal1 spacing?
plz help me!
and thanks in advance !
sevid
hi,everyone
i simulate my design with an off-chip memory with these steps below:
1.if my memory is defined as following:
module memory(...);
...
reg [31:0] mem [07:00];
...
2.then i initialize it in my testbench:
$readmemh("mem0.in", memory0.mem);
3...
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