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Recent content by senthilos

  1. S

    Looking for information about False Path Delay

    Re: False Path Delay Hi Dinesh, Read the article below. https://chipverification.blogspot.com/2008/03/multi-cycle-path.html Thanks Senthil
  2. S

    division and modulo in synthesis

    Hi, How do I implement division and modulo operations if my synthesis tool doesn't support these. All suggestions are welcome. Thanks Senthil
  3. S

    multiplication without using * operator in verilog

    Syswip and amraldo, Your solutions seem quite different. Thanks! What do you mean by design circuit using ANDs and XORs? You mean to draw the entire multiplier circuit using logic gates?
  4. S

    multiplication without using * operator in verilog

    Hi, I got an interview question yesterday on multiplying a 10 bit number with a constant. Ex: a[9:0] * 24. The interviewer was expecting a answer without using the straightforward * operator. Can anyone throw me more light on how to do this multiplication without using * operator? Thanks Senthil
  5. S

    detecting number of 1's in a 8 bit data line

    Hi FVM, The combinational logic options looks good. Can there really be a sequential logic solution for this, because the o/p is expected for each clock cycle. Thanks Senthil
  6. S

    detecting number of 1's in a 8 bit data line

    Hi GrandAlf, I don't understand what is meant by "common the outputs". Can you please brief a little more on that. Thanks Senthil
  7. S

    detecting number of 1's in a 8 bit data line

    Hi fcfusion, You have posted a link to a software solution which is good. My question is to find a solution at the gate level (using adders, mux, FlipFlops, etc). Thanks Senthil
  8. S

    detecting number of 1's in a 8 bit data line

    Hi, Yesterday I got this design question in an interview. How do you detect the number of 1's in a 8 bit data line? There is a clock running. At each clock, the output should display the number of 1's(the count) in the data line. The interviewer expected me to design a hardware circuit at...
  9. S

    interview qstn on comb ckt to remove less time pulse

    I believe you can build a comb logic to monitor the input every 1ns and have a counter running. If for 5 consecutive sampling if the input is sensed as HIGH then the output should be driven HIGH for 5ns and reset the counter. Otherwise the output should be driven LOW and reset the counter...
  10. S

    Circuit for Clock Divide by 5 and 50 % duty cycle (urgent)

    Re: Circuit for Clock Divide by 5 and 50 % duty cycle (urgen Hi Arvind, What do you mean by 'Analyses all the waveforms from the flops O/P'? I didn't get that point straight. Added after 2 minutes: Hi Koggestone, In your verilog code shouldn't CLKA be computed as assign clkA =...
  11. S

    interview question.combinational circuit frequency division

    Re: interview question.combinational circuit frequency divis 1) Double clock frequency. An EXOR gate with one input being the original clock signal. The other input is the clock delayed by cycle_time/4. The delay can be achieved by buffers. The output is now double the clock frequency. 2)...
  12. S

    interview question on setup...please solve

    Hi TA, I believe you are trying to say hold <propagation so that the Q! signal stays stable at D input. Is that right?
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