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Recent content by senilicus

  1. senilicus

    How to open .brd PCB file

    The Cadence Allegro Viewer does not include DbDoctor. You need a Cadense Allegro License if you want to update your design to the latest version/format. We have experienced the same problem, but there is a simple solution. Use an old version of the Cadence Allegro Viewer! In this case...
  2. senilicus

    Xpedition edm cockpit

    As we do not use EDM, it is hard to me to point you into a direction. We use Library Manager for managing blocks, and that is straight forward.
  3. senilicus

    Xpedition edm cockpit

    When the list is empty, there is no Managed Block that needs updating.
  4. senilicus

    dielectric thickness between signal and return planes

    There is no simple answer to this. There are several factors that play a role here. The number of layers and the required finished board thickness. The pcb material and it Dk. Required trace widths (manufacturing) and thickness You can play around with the numbers in Saturns "PCB Toolkit".
  5. senilicus

    What are the most important IPC standards for new PCB designers?

    My two cents; IPC-2221, Generic Standard on Printed Board Design IPC-4101, Specification for Base Materials for Rigid and Multilayer Boards IPC-7251, Generic Requirements for Through-Hole Design and Land Pattern Standard IPC-7351, General Requirements for Surface Mount Design and Land Pattern...
  6. senilicus

    How does one determine the track width for "slow" signals?

    Simply use your fabricator's recommendations on width/spacings. Most of them have this available as a download. Have a look at the attached file. (as an example)
  7. senilicus

    How do we match the timing of CLK and DQS signals in DDR

    https://www.google.com/search?client=opera&q=timing+of+CLK+and+DQS+signals+in+DDR3&sourceid=opera&ie=UTF-8&oe=UTF-8
  8. senilicus

    PCB via hole

    https://saturnpcb.com/saturn-pcb-toolkit/
  9. senilicus

    Any idea why the filled the holes for my component's pins?

    Looks like a missing file to me. Slotted holes are not in the drill file. It is a separate file. If you do not supply that file, you won't get the slots. we have had the exact same situation.
  10. senilicus

    How to check via is closed by solder mask or not by using Allegre free physical Viewer

    Turn on the soldermask layer, what you see is what you not get! iow, in most cases soldermak is show as a negative layer, you see the openings in the mask
  11. senilicus

    [Moved] HDMI routing

    Length matching will only work when the signals are on the same layer (or very slow). In all other cases you have to use Time Of Flight (TOF) as Marce already indicated.
  12. senilicus

    what differentiates vias to micro-vias in electronics?

    A Microvia is basically a very small via. Most PCBs now days are multi-layer boards. Vias are used to make connections between each layer of the printed circuit board. Microvias, as the name suggests have a smaller diameter and thus take up less board real estate and leave more space for...
  13. senilicus

    Interplane Capacitance

    In general, from an EMI view, it is not a good practice to put a signal layer between the PWR and GND plane. The energy is not in the copper, remember. It is between the planes, For high speed signals this can be the root cause for problems. The closer the two planes are, the higher the...

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