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Recent content by semiartist

  1. S

    latch up - which device induces latch-up?

    latchup iv curve usuasly, the latch up is due to layout, the figure u posted, i think, the p+(bulk of nmos) should be placed close to nwell, that's to say, it should be placed at the right side of nmos.
  2. S

    The effact of W and L for vth of MOS transitor

    vth vs l I don't think so! Actually, Vth is almost nondepent on L or W when L or W is large (not short or narrow MOS). However When L or W decrease, the Vth would increase. You will see the reason and the formula on Neman's book, sorry, I can't remember the exact name of the book, it's on...
  3. S

    1/f noise of PMOS and NMOS

    Chopping and auto-zeroing are useful techniques for handling 1/f noise in amplifier circuits (**broken link removed**). Hi roadbuster, I can not access the link, could you please give me other link or send it to my email address? my email: semiartist@yahoo.com, thanks! BR, Alex
  4. S

    New To Layout - request for resources

    New To Layout Please search for "Layout" in this forum, they are many many threads
  5. S

    How to connect the 3rd terminal resistor for TEC?

    3 terminal resistor? I ever saw 3 terminal capacitor, same principle as the resistor? Thank you!
  6. S

    explanation of basic function of vco

    vco There are ring VCO, LC VCO and transformer feedback VCO, etc. But the basic principles are same, just voltage to control the frequency. I think new life was saying " turning range", together with phase noise, they are the most important parameters. Sorry, i can't give the details...

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