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Recent content by semesu

  1. S

    pseudorandom noise generating with matlab

    hi, I wanna generate pseudorandom noise with matlab and gıve its output to 10 fır bandpass fılter, how can I do this with matlab? I did not fınd any codes about ıt thanks
  2. S

    Help me generate PWM in Verilog HDL

    pwm waveform in vhdl code I have found new codes. I have sımulated it by moudle sımulator. and I get some results but I can nor understand whether they are rıght or not. can you help me to understand this? module PWMMain(DC,CLK,Q); input [7:0] DC; input CLK; output Q; wire CLKO; //...
  3. S

    Help me generate PWM in Verilog HDL

    pwm en verilog 25 Dec 2008 15:52 Re: PWM in Verilog HDL -------------------------------------------------------------------------------- I think, the correct result is different: out accu[7:0] in // I don't understand the numbers below what are they for? 0 0 70 0 70 70 0 140 70...
  4. S

    Help me generate PWM in Verilog HDL

    pwm using verilog I can not understand exactly what you mean,can you explaın more clear? thanks
  5. S

    pwm and one bit dac in verilog

    dac verilog code Hi, I have a project on pwm in verilog programming language. "pwm and one bit dac". The aim of this project is to convert the dıgıtal data to analog. Ihave found codes. I am usıng xilinx spartan 3E kit module PWM(clk, PWM_in, PWM_out); input clk; input [7:0] PWM_in...
  6. S

    Help me generate PWM in Verilog HDL

    sigma delta pwm verilog is there anyone help me?
  7. S

    Help me generate PWM in Verilog HDL

    fpga verilog pwm Hi, I have a project on pwm in verilog programming language. "pwm and one bit dac". The aim of this project is to convert the dıgıtal data to analog. Ihave found codes. I am usıng xilinx spartan 3E kit module PWM(clk, PWM_in, PWM_out); input clk; input [7:0] PWM_in; output...
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