Recent content by sebas

1. Don't care value during simulation

Hi, What happens to "X" - don't care values during simulation? To understand what I'm saying here's an example: in a testbench there's the following statement: we = 1'hx; then, lines after there's the following test: if (we) // do something// (there's no else branch). What's the result of...
2. Analog and digital switches/ maximum input signal frequency

Hi, Thanks for the reply. Any link to an article that discusses how to calculate the maximum rate?
3. Analog and digital switches/ maximum input signal frequency

That doesn't really answer my questions. Why are those circuits good?
4. Analog and digital switches/ maximum input signal frequency

Hi, Two beginner's questions: 1. What is the differences between an analog IC and a digital IC switch? 2. How can I find the maximum frequency for the input signal of a switch? I looked through the datasheet of a switch and I couldn't find a parameter that can tell me this. I want to use a...
5. [SOLVED] pull up value on signal that has driver

Hi, I see that there are a lot of schematics where there are pullups on pins that also have a driver. Can you do this with any signals (i usually see it on reset signals)? How weak has the pullup so the driver can still make the signal 0? Thanks
6. [SOLVED] DC/DC converter input current

Ok, I understand the efficiency, I know what 80-90% efficiency means but what does this have to to with input current? What is the input current after all? I guessed it is the maximum current that being fed to the converter doesn't damage the device, am I wrong?
7. [SOLVED] DC/DC converter input current

Hi, Newbie's question, I was looking at the following DC/DC converter's datasheet: https://www.murata-ps.com/data/power/uwr15wa-series.pdf and I see that there is a parameter called Iin. I'm guessing that this is the maximum input current for the device, right? Why is this dependent on the...

I'm working on Xilinx too. So, if I have a design constraint that sets the max frequency to be the frequency of the whisbone clock and the design passes synthesis without errors then I'm guaranteed stable work?

I don't want to use different edge sensitive triggers I just suggested that as a solution if there would be problems. But, I know realize that my question was a bit stupid, the fact that both transfers (read and write) occur in the same clock domain it's enough to guarantee the data is valid, right?

Hi, thanks for the response. maybe metastability was not the perfect word, I know the metastability occurs in multiple clock domain design. My question was if I have something to worry about in a design where I have the same clock (both wishbone and SPI work on the same clock).

Hi, In my code I have a register that is written with data read from SPI (register is 32bit and loaded after all the 32 bits have been read from SPI in a temp register). On the other side the register is read by the wishbone interface. My question is: do I have to worry that the data can be...
12. input never used error, although it is used

Hi, I have the following code: always @(posedge clk) begin if (!rst_n) begin push_button_sts_d1 <= 1'b0; push_button_sts_d2 <= 1'b0; push_button_sts_d3 <= 1'b0; pb3_rst_d1 <= 1'b0; pb3_rst_d2 <= 1'b0; pb3_rst_d3 <= 1'b0; pb1_rst_d1 <=...
13. access GPIO. Southbridge's registers

Ok, so how do I find the address allotted to it?
14. Question about the code for register file access

Hi, A newbie's question, in the following code: module reg_file ( input wire clk, input wire wr_en, input wire [1:0] w_addr, r_addr, input wire [7:O] w_data, output wire [7:Ol r_data ) reg [7:Ol array_reg [2**1:0] ; always @(posedge clk) if (wr_en) array_reg [w_addrl <= w_data; assign...
15. access GPIO. Southbridge's registers

I don't understand what you are talking about. Can you be more specific, please.