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What happens to "X" - don't care values during simulation? To understand what I'm saying here's an example:
in a testbench there's the following statement:
we = 1'hx;
then, lines after there's the following test:
if (we) // do something//
(there's no else branch). What's the result of...
Two beginner's questions:
1. What is the differences between an analog IC and a digital IC switch?
2. How can I find the maximum frequency for the input signal of a switch? I looked through the datasheet of a switch and I couldn't find a parameter that can tell me this. I want to use a...
I see that there are a lot of schematics where there are pullups on pins that also have a driver. Can you do this with any signals (i usually see it on reset signals)? How weak has the pullup so the driver can still make the signal 0?
Ok, I understand the efficiency, I know what 80-90% efficiency means but what does this have to to with input current? What is the input current after all? I guessed it is the maximum current that being fed to the converter doesn't damage the device, am I wrong?
Newbie's question, I was looking at the following DC/DC converter's datasheet: https://www.murata-ps.com/data/power/uwr15wa-series.pdf and I see that there is a parameter called Iin. I'm guessing that this is the maximum input current for the device, right? Why is this dependent on the...
I'm working on Xilinx too. So, if I have a design constraint that sets the max frequency to be the frequency of the whisbone clock and the design passes synthesis without errors then I'm guaranteed stable work?
I don't want to use different edge sensitive triggers I just suggested that as a solution if there would be problems. But, I know realize that my question was a bit stupid, the fact that both transfers (read and write) occur in the same clock domain it's enough to guarantee the data is valid, right?
thanks for the response. maybe metastability was not the perfect word, I know the metastability occurs in multiple clock domain design. My question was if I have something to worry about in a design where I have the same clock (both wishbone and SPI work on the same clock).
In my code I have a register that is written with data read from SPI (register is 32bit and loaded after all the 32 bits have been read from SPI in a temp register). On the other side the register is read by the wishbone interface. My question is: do I have to worry that the data can be...
I have the following code:
always @(posedge clk)
push_button_sts_d1 <= 1'b0;
push_button_sts_d2 <= 1'b0;
push_button_sts_d3 <= 1'b0;
pb3_rst_d1 <= 1'b0;
pb3_rst_d2 <= 1'b0;
pb3_rst_d3 <= 1'b0;