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Recent content by seanyang

  1. S

    Questions about Power Management IC design

    Re: Power Management IC hey joe, As you questions, i have some answers. 1.Q: Is it part of analog ic design field? A: Yes, it is. As every portable product need supply. And for the cost issue, this part has been designed to IC field. 2. Q:Could you please advise any books for a...
  2. S

    Generating the bias voltage of an op-amp

    Re: Bandgap Reference All right, just using the architecture like LDO form. But must sure no cuurent drive from out pin. Or you will have stability issue.
  3. S

    Can Monte Carlo simulation be performed to analog_extracted?

    Re: Monte Carlo Yes, it can be perofrmed to analog_extracted. The way just like schematic monte carlo simulation, But the netlist file includes more parasitical capacitors and resistors.
  4. S

    CMFB in a cascode differential pair

    No matter you connect to bias or point A, the concept is to control the current if the Vout1 and Vout2 rise(fall) and restoring the output CM level. Ref: Design of Analog CMOS Integrated Circuit "Razavi" thx~~
  5. S

    Help! circuit problem!

    Dear overmars, I tihnk the module D is the CMF (common mode feedback) circuit. If your want use differential out, you must add it. If your want know detail about CMF circuit, you can see any one analog book. thx~~
  6. S

    How can I calculate the RC delay in this configuration?

    Re: RC delay Show me your proggate node voltage.
  7. S

    How to measure slew rate(SR) for fully differential OTA?

    Using the first method and add the Rload & Cload. Give it a VPLUS voltage (from 0~vdd). And you will see the output will follow the input with a slop. The 10% to 90% slop is you SR.[/img]
  8. S

    Help needed about fully folded cascode OTA with PMOS input

    Re: Help needed about fully folded cascode OTA with PMOS inp Could you post your circuit and how you simulate it.
  9. S

    Fully folded casode op amp design procedure.

    You can see the "CMOS Analog Circuit Design" Allen book. The section 6, there has what you want.
  10. S

    TSMC 0.35um ESD Size ??

    I think you can see "ESD in silicon integrated circuit" book. You can find your answer.
  11. S

    Op-amp recommendation?

    YOu can go to the wedsite like TI, HITCHI, Analog Device, NEC etc... It's too much!!
  12. S

    TSMC 0.35um ESD Size ??

    tsmc 0.35um esd The RC decided the time you want to discharge the voltage. And the last NMOS should be very big for the voltage you want discharge. You can decide the size by simulation.
  13. S

    help needed in designing fully diff amp very urgent plz repl

    Re: help needed in design of fully diff amp very urgent plz It doesn't makesense of the GBW=450MHz. It's too large. If your GBW=450MHz then your SR will more than 20 v/us. Since your GBW=450MHz, I think your differentail pair input would be very very big. (Consume large area and power). If...
  14. S

    Question: amplifying signal by current mirror

    You can use an ac current source(like, DC=10u, Amplitude=10mV, Frequency=10KHz) as your Iref. Then you will see the change in another site.
  15. S

    how to find i/p and o/p voltage swings(max and min)

    Try this:
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