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Recent content by seahs

  1. S

    standard cell design engineer VS product engineer?

    which one got better future? It seems to me that standard cell design engineer does not have much room for promotion, since standard cell characterization may have a standard process? I am fresh graduate and does not know much about those jobs. Pls advice. Thanks in advance.
  2. S

    how large should the output pad driver be to achieve a speed of 500MHz

    what are the typical capacitance for output pad, off chip connection wire and input of the oscilloscope? I am quite new to IC fabrication and unsure about how many times larger I should size the output buffer, compared to the minimum sized transistor. BTW, I am using STM65nm
  3. S

    Placement&route of memory cells using cadence encounter

    Since memory cells are arranged in a very regular structure, is there a special way to place&route the memory cells? or it is the same way as standard cells
  4. S

    How many pins can a circuit have?

    Is it as many as I can draw in the layout? Thanks.
  5. S

    what are the capacitance of digital I/O pad in 65nm?

    Does it vary a lot for different fabs? Thanks.
  6. S

    Anybody have the lastest Cadence Abstract Generator User Guide?

    student can not access sourcelink.com Thanks.
  7. S

    nanosim memory design

    how to include bitline metal layer capacitance in memory design using nanosim? It seems the total bitline cap is very small in my design, about 100fF for a bitline with 1024 memory cells connected in 130nm. I am wondering if the metal layer cap is included. Thanks for any suggestion.
  8. S

    6T/8T SRAM CELL layout with row controlled VDD and VSS

    In the LS(lithographical symmetrical) sram cell layout, vdd/vss has to be shared by the cells in the adjacent rows. I've read some papers talking about sram where the vdd is controlled row by row. I just wonder how the layout is done. Thanks for any suggestion;-)
  9. S

    what does the drain capacitance of a cut-off mos transistor consist of?

    and what percentage does each individual normally take in deep sub-micron,say 65nm?
  10. S

    measure transistor current -nanosim

    Anybody knows how to measure current of X1 as follows, it seems nanosim can only measure elements starting with M, C...and so on .SUBCKT INV1X1 A Q **INV Part X1 Q A VDD! VDD! PFET L=120E-9 W=560E-9 X2 Q A GND! GND! NFET L=120E-9 W=160E-9 .ends
  11. S

    nanosim power analysis

    Just find that in my design the total average power is less than half the summation of individual average block power, how can that happen? all suggestions are welcom :?
  12. S

    Problem in characterizing the Vth in Cadence Calculator

    I am going to charaterize the Vth using the following equation: sqrt(2*I) = (Vgs-Vth)*sqrt(K*W/L)..... and I set up the variable sqrt(2*I) in the ADE. while the following error occured: *Error* Evaluating expression (sqrt((2 * IDC("/M0/D")))). *Error* ("times" 2 t nil ("*Error* times...
  13. S

    how to do 1/f noise characterization in Cadence?

    any suggestion? thanks

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