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Recent content by Scrts

  1. Scrts

    Arm cortex m3

    use eclipse
  2. Scrts

    [SOLVED] BT656 8bit conversion to 10bit

    Solved: assert LSB bits to MSB bits. E.g.: Data[1] <= Data[9]; Data[0] <= Data[8]; Works fine.
  3. Scrts

    can FPGA kit (spartan 3e) be brought to India by someone?

    I could sell my own Spartan-3E kit + digilent expansion board + mine home made 7seg addon board + 100MHz oscillator with DIP adapter. Mail me mailsoc@gmail.com if interested.
  4. Scrts

    Frequency satbility of crystal oscillator

    It will add jitter, so I would say DCM is not a way to go...
  5. Scrts

    How to generate an 8 bit random value ?

    I don't know the compiler, but most usual are rand() or random(). It will be pseudo-random number however.
  6. Scrts

    instaniatinga a module at every clock edge

    You can't instantiate a module dynamically. Think of the hardware, not the software. You can instantiate the same module as many times as Your FPGA fits. So use the same module and change input parameters or instantiate the same module more than one time assigning different signals.
  7. Scrts

    FIFO Xilinx Core Generator

    It is more useful to use almost_full or almost_empty flags as data is never corrupted or gone. This also can be achieved by using usedw[width-1:0] output. I am talking about Altera DCFIFO here, but I am sure, the same is on Xilinx.
  8. Scrts

    FIFO Xilinx Core Generator

    No, it just becomes more possible to get fifo empty or full.
  9. Scrts

    FIFO Xilinx Core Generator

    When You use DCFIFO (dual clock fifo). When the read or/and write clocks are different frequency, You can check the full/empty flag and control the write and read flags accordingly.
  10. Scrts

    Xilinx ChipScope Tutorial

    Maybe anyone has seen or made similar manual for signaltap?
  11. Scrts

    Clock regeneration for video signals

    Thats a great idea. Usually, a VCXO (or else called VCO - Voltage Controlled Oscillator) is used for this purpose. However, I use the smallest Cyclone II, which has only two PLLs, so I drive both PLLs with the same 27MHz clock. The outputs are: PLL1 - 27MHz(for the whole logic), 54MHz(for ASI...
  12. Scrts

    Clock regeneration for video signals

    Hello, the question is actually about video signals, but I suppose it could be common in FPGA designs, where crossing clock domains matters. I am trying to use Altera SD-SDI core in receiver mode, which receives 270MHz SDI signal, by sampling it 337,5MHz clock, so the output is 10bit parallel...
  13. Scrts

    Help me implement high accuracy system with XUP boards

    Re: Help with XUP boards I am not sure about Virtex-II, but afaik it is not supported by the newest version of ISE, so it would be better to use Virtex-5, because the newest ISE should support VHDL-2008 and new math libs. Usually, for simple maths numeric_std lib is used, but there are more...
  14. Scrts

    [SOLVED] BT656 8bit conversion to 10bit

    Hello, I need to create SDI(serial digital interface) output from BT656 signal, which is 8bit wide. The problem is, that SDI is 10bits wide, so I need BT656 8bit conversion to 10bit. Conversion of EAV and SAV sequences are clear: FF -> 3FF 00 -> 000 00 -> 000 But what about all the further...
  15. Scrts

    VPN setup on Windows XP SP3

    Well Windows XP has built-in VPN server, so I connect to the office PC directly, without using any software. The current solution of having the office PCs IP is to use remote desktop, but it has latency and isn't fast responsive...
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