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Well, actually I am still not an expert because in the end I decided to do all the floating point stuff on the computer by sending it back and forth via an FTDI USB chip.
I think the best way to do it is to "manually" copy your bits to the appropriate location of the floating point number...
It works now. The GND and VCC pins of the PROM chip where not correctly soldered. But I have a new problem now. The code runs fine if it is programmed directly to the FPGA but if it is start up in master serial mode via the PROM, it doesn't work. DONE never goes high and the CCLK keeps clocking...
I can't get the boundary scan to detect my devices. I have a homemade board with a Xilinx Spartan 3E (xc3s100e) and a Xilinx PROM attached (XCF01SVOG20). The JTAG device I use is a Digilent XUP USB-JTAG Programming Cable. The scan only finds one device instead of two and it is is labeled...
xilinx coregen
Yes indeed, I figured that one out (see my post above). I also found out how to use signals in a function: don't use a function but a procedure. That pretty much solves all these problems.
floating point xilinx
Thanks, indeed I have to adhere to the floating point format.
Anyway, how can I simplify those operations to make the computation to work (enable the core with ce, wait until it is ready, etc) ?
Like with a function.
ise webpack floating point
Ok, here are some new findings:
To get the FPU to work, this needs to be done (I think):
variable vector1_from_SDRAM: std_logic_VECTOR(7 downto 0);
variable vector2_from_SDRAM: std_logic_VECTOR(7 downto 0);
variable temp_vector...
coregen floating point
Ok, I found out that I have to place this code in the architecture before "begin:
(from the core generated *.vho file)
component float
port (
a: IN std_logic_VECTOR(15 downto 0);
b: IN std_logic_VECTOR(15 downto 0);
clk: IN std_logic;
result: OUT std_logic_VECTOR(15...
xilinx floating point
I can't figure out how to implement the Xilinx CoreGen generated code. I want to do some floating point operations (let's say a division). I am only interested in synthesizing my vhdl code and making the FPGA actually doing something, simulation is not used.
This is what...
I am trying to assign the pins for my Spartan 3E FPGA with PACE (ISE WebPack 10.1) But PACE doesn't pre-assgin any pins. The "Loc" field is blank for all fields. If I input a pin K13 in the Loc field, it displays the error: Invalid action: K13. All Loc fields contain a drop down list but the...
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