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Recent content by saurabhs

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    Help me design a 01020102 counter using 2 D flip flops

    01020102 counter 2 DFF Lets say Q0 Q1 is output of these DFFs D0 and D1 is input of DFFs D0=Q0 (XOR) Q1 D1=(NOT) Q1 Output of Machine lets say Z0 and Z1 Z0=Q0 (AND) Q1 Z1=Q0' (AND) Q1 Z0,Z1 Will be 00 ,01,00,10,00,01,00,10....
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    Problem with a two bit fulladder homework for ISE Xilinx

    2-bit fulladder They use sum [4:0] for a carry out bit. u can use sum [3:0] and a different carryout bit. For a 2 bit full adder u have to have 4 half adder. so i feel a[1] and b[1] will use in another half adder. Isn't it.I m getting u correct.
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    Verilog how to lock value?

    If i understand correctly ur prob I think just change the sensitivity list Always @( signal on which u want to execute always block )
  4. S

    Problem with a two bit fulladder homework for ISE Xilinx

    2-bit fulladder use Add_half_0_delay M1(w1,w2,a[0],b[0]); like this It may work
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    How to define global variable in verilog?

    Hi all I wanna define global variable in verilog so that i can use them in different module. How it can be done. Thanks in advance.

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