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why global skew not local skew is of importance in clock tree building
Hi all,
im using cadence encounter. For CTS we give tool, clock tree spec file that has inputs like min phase delay , max phase delay and max skew paramters etc. My understanding is that Max skew parameter that we are...
hi all
im doing my proj sig del CT
fs=6.144Mhz
signal bandwidth is 24000 Hz
order 2
Nrz pulse feedback 1 bit quantizer
im implemnting ota in 180 nm tech
vdd=1.8
vss=0
i designed the ota for input common mode at 0.9v
wat shud be the input given for the modulator.
A sin wave with .9 dc and some...
my load capacitance is 4 pF... can u tell me hw current the relation goes?...im concerned abt swing so i put a cs stage as second stage
and for gain i put pmos input telescopic ....bothh Cc and Cl are 4 pF
hi...
im trying to simulate sigma delta adc in cadence at behaviral lvel....
wen i used ideal integrator block in ahdl lib in cadence results came gud
bt wen i try puting opamp based Integrator (used ahdl lib opamp wid Appropriate R & c values) i cudnt get the results at all...some unexpected...
im designing opamp wid gain > 50db UGB= 100Mhz
im going for two stage opamp...
first one is telescopic pmos input
second one is AB class ...
my slew rate is 25v/us
wid that slew rate im able to arive I bias to 100 uA at the output stage
bt im confused wat bias current shud i take for first...
hai,
Its very useful suggestion and thanks alot...
But what can be the slew rate specification in particular for the first stage OTA and second stage OTA....for my first and second stage integrators.?
Iz it enough to take for UGB alone wid out slew rate....?
thank u
my spec goes lyk this:
Continuos time sigma delta ADC
order=2
fb=24khz
osr=128
target bits=12
how shall my integrator spec should begin wid lyk UGB,gain, slew rate of the OTA in integrator? help me out plz
hi....im designing a Sigma delta 2nd order...CIFF architecture....
in literatures they hav suggested to use more linear and low noise first integrator for better performance...so they said first integrator is a power hungry one...
bt where the difference in design of low noise cum low power OTA...
hi...my signal BANDWiDTH is 25 khz...n my sampling frequency is 100 MHZ...i need to determine R and C values of integrator... for the first and second integrator ...im confused in choosing them.... and how abt the constraints on first and Second OTA of on gain n bandwidth....
can u plz help me...
Im designing an OTA with 0.18um Umc tech....a total current of 400 uA is used...when i plot gain in db vs input common mode level... im gettin a very sharp spike at 0.9v and the gain is significantly reducing after and before 0.9v... the response i hav got is correct or not... if nt correct then...
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