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Actually we will perform Design Exploration early in your synthesis flow, at this stage we will check for timing violations by applying some constraints,
You can reasonably expect advanced compile strategies to fix violations that are 10-15% over timing, if all the timing goals are meet then you...
Verification:-Is a process where you verify the functionality of your design ( RTL, to be more precise) before synthesis and also after synthesis (Gate level Design Synthesis), using Hardware Verification Languages. On the other hand,
Validation:-Is just validating your chip with some typical...
yes,you can't say verification is completed for design and you can say only that i have done verification of some percentage(%)...
the percentages based on your verification strategies. like if you done branch coverage you can say how many branches have you exercised successfully, if you done...
Hi oratie,
Thank u......
i heard that after fabrication of test chip the setup/hold values are extracted practically. is it true...
and one more question that if the circuit passes for different values, which one will be considerable...
hi,
am sorry,
then you need to define a variable pointer_difference, compare the both wr_add_ptr and rd_add_ptr and store the difference in pointer_difference so that you can estimate weather FIFO is almost_full or almost_empty.
go through this link you may gain more knowledge about FIFO...
hi,
In your memory(FIFO) if the read address and write address are equal then the FIFO is empty"wr_add[n:0]==rd_add[n:0]" and where as in Full case, you should ~the MSB of write address and then compare the wr_add and rd_add if both are equal then you can say FIFO is full else FIFO is not...
i completed my graduation in the stream of electronics and communication engg.
i want to do MS in VLSI @USA.which is best university that can i found in the US.after completion of MS is there any chances to get the job in US? can u suggest some suggestions to me:oops::lol:
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