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Recent content by satanam

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    Unable to generate Fabrication drawing in allegro 16.3 in .art format

    Hello Shabu, Thanks for the response. I had given value to undefined line width. Hello Ricky, Thanks for the response. I had added photoplot line and also added required layers to fab drawing. I have also increased the "film size limit", but still I am unable to see the drill legend, fab notes...
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    Unable to generate Fabrication drawing in allegro 16.3 in .art format

    Thanks for the inputs! I had already placed the NC legend from artwork and had selected the required subclasses under the fab layer, but unfortunately when i hit "create artwork" buttom, all I get in the .art file is the drill symbols. I still don't get the drill legend table, fab notes and the...
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    Unable to generate Fabrication drawing in allegro 16.3 in .art format

    Hello All, I am trying to generate fabrication drawing in .art format in allegro 16.3. I have used a Dsize fab symbol in Class Drawing format -> subclass outline. Also added assembly notes and layer stackup information in Class Drawing format(outline, title block). When i try to generate the...
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    RF integrity check of multilayer PCB using Cadence Allegro

    Thanks CKS ---------- Post added at 16:33 ---------- Previous post was at 16:33 ---------- Thanks Marce.
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    RF integrity check of multilayer PCB using Cadence Allegro

    Hello Marce, It is a RF design. Thanks, Satanam
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    RF integrity check of multilayer PCB using Cadence Allegro

    Thanks for the reply CKS. Yes I need to check the overall signal integrity of my design with respect to RF design rules. If Allegro cannot do it, can you please tell me which tool does it? Thanks, Satanam
  7. S

    RF integrity check of multilayer PCB using Cadence Allegro

    Hello, I need to know is there a way to check an already designed multilayer PCB to undergo RF integrity check using Cadence Allegro 16.3? In other words, is there an option in Allegro that will check whether the board satifies all the rules set for RF design? Thanks for the help. Satanam
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    Applying constraints to track length in Orcad layout

    Thanks Kabaleevisu!
  9. S

    Applying constraints to track length in Orcad layout

    Thank u Marce. I guess I'll have to move to Allegro.. Its really strange Orcad layout does not support one of the most important feature in high speed designing.
  10. S

    Applying constraints to track length in Orcad layout

    I am designing a high speed board. I want to maintain equal track length of the buses to maintain skew. Can anyone please tell me how this is done in Orcad layout? I am unable to apply length constraint in Orcad layout. Thanks.
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