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Recent content by sarit8

  1. S

    How to implement derivative, and create a delay of dozens of clock cycles?

    down vote favorite I have uart entity which have the following signals (I write only the relevant - for tx) -- The output data: 8 bit - this is the UART receiver -- Data is only valid during the time the STB is high -- Acknowledge the data with a pulse on ACK, which is confirmed by -- revoking...
  2. S

    Using uvm_config_db to nitialize/pass params from the sequence to the transaction?

    I have the following transaction: typedef enum {READ = 0, WRITE = 1} direction_enum; //Transaction class axi_transaction extends uvm_sequence_item(); bit id = 0; //const bit [31:0] addr; bit [2:0] size = 0'b100;//const direction_enum rw; bit [31:0] transfers [$]...
  3. S

    Timing diagram for write and read transaction in AXI4

    Re: AXI4- samplinf of WRADDR and WDATA Yes but why? how? How can we can send the data before the protocol "knows" the address?
  4. S

    Timing diagram for write and read transaction in AXI4

    AXI4- samplinf of WRADDR and WDATA Why WRADDR and WDATA can be sampled in the same cycle? For example see the AXI4 Write Transaction Multiple write, not burst timing diagram (page 20) in: http://xilinx.eetrend.com/files-eetrend-xilinx/forum/201509/9208-20395-creating_and_adding_custom_ip.pdf
  5. S

    Timing diagram for write and read transaction in AXI4

    I have to find a diagram with all of the signals like AWSIZE, AWLEN, ASTRB WLAST etc.
  6. S

    Timing diagram for write and read transaction in AXI4

    I have aleady read it. There are just 2 basic diagarm (general transaction), and one more for barrier ntransaction,
  7. S

    Timing diagram for write and read transaction in AXI4

    Lol:) I have already dine it, but have not suceeded to find something with good explenation yet.
  8. S

    Timing diagram for write and read transaction in AXI4

    Where can I find a timing diagram for write and read transaction in AXI4 (Including write channel response)?
  9. S

    How to read a file in system verilog into transaction prototypes?

    I have a file with multiple lines with the following structere r,ACFE13D5,00000000 w,FE1234AC,00000000 The mid value is hexa adreess, and the last value should be data with lengh of 32 bit(also hexa). What is the simple way ro read such a file and get the values into the following transaction...
  10. S

    AXI4- explenation regarding transaction, data transfer, burst and beats

    I'm little confused refarding the relationship between the above concept. Does burst is just a type of AXI transaction> Can it take more the one clock transaction? What is exactly a beat? does it contain address and data?
  11. S

    [moved] Tutorial of BUS structure and functionality

    I have searched for UVM AXI4 BFM in github, but didn't find. If you remember the name of the project it will elp me. I have already read the AXI4 specifications from arm, but I wanted to read or see some tutorial which may help with some unclear issues. I try to implement a transaction and...
  12. S

    [moved] Tutorial of BUS structure and functionality

    I have to create a test bench for oyr project which contains AXI4 BUS. It's the forst time I'm dealing with BUS. Where can I find good tutorial of BUS structure and functionality, and after for AXI4. I have to understant it well for implementing a driver (UVM) fot the axi bus (master).
  13. S

    [moved] Creating test bench for AXI bus

    I have to creat test bench to my project which contains AXI bus. I start to write the interface and the transaction for write and read. I read the following blog: https://blog.verificationgentleman.com/2016/08/testing-uvm-drivers-part-2.html?showComment=1471877179631#c7809781639091671746...
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