Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by saraiust

  1. S

    design an 8-bit processor by VHDL

    Hi everybody I need a very soon help.. I have to design a 8-bit processor in VHDL. Is there anyone who can give me some useful links for datapath? I know that it may be on opencore, but I need some guydance in finding proper analyze for this project and proper datapath for that. it is very...
  2. S

    Serial port Module by DCM in VHDL

    Hi, I am new at edaboard and VHDL, I need a very soon help in implementation of a serial port, can you help me? I have to make a module with serial in and out and parallel in and out. which recieve parallel data and send by serial port and viceversa. It of curse need a DCM module, which...
  3. S

    How to use FIFO component in VHDL?

    Re: using FIFO in vhdl hi i am new at vhdl too!! and i have to make a fifo, could you help me in that? asap? :cry: thanks !
  4. S

    vhdl fifo ram with two clks - help needed

    thank you! but this is exactly my problem, cas i dont know how to make a controller... :cry:
  5. S

    vhdl fifo ram with two clks - help needed

    but with one array, if one port start to write on one address and the other port start to reed that address, what do i have to do then?...
  6. S

    multiply accumulator in vhdl help needed

    multiply accumulator hi everybody, I need to make a multiply accumulator in vhdl and i dont have any idea.. can you help me to find an architecture for multiply accumulato with simple gates, like and,nand,or... --asap-- i mean a simple architecture to understand how to simulate that. thanks!
  7. S

    amount of parallel process in vhdl

    process in vhdl hi do we can have 2 process in one architecture? how do they work? can you tell me more about process in vhdl? thx.
  8. S

    vhdl fifo ram with two clks - help needed

    vhdl fifo ram with clks hi i'm new at vhdl programming, and I want to learn it as possible as I can. I have to make a FIFO ram, with 2 clks, but I don't know any special thing about 2 clks in one ram,and of curse I have to make a ram with read and write ports, and this one needs 2 clk-- i...
See more

Part and Inventory Search

Back
Top