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Re: ELECTROMIGRATION
Dear friend ,
Signal nets are always bi directional only. in signal there will no electro migration instead there will be metal migration due to thermal and joule heating effect.
where as electromigration occurs in P/G nets.
hope i have expalined i not catch me
santu
Dear vlsi technology,
consider metal1 , consider a net passing in metal1,
let one end of the net is connected to gate of the transistor the other end must be connected to either source or diffusion they twomust be connected thro metal1.
gate is the receiver and drain/source is diver . so...
dear Vlsi Technology,
If u palce diode near the gate . the lenght between gate and diode is less the maximum length will be between diode and floating end hence maximum charge will accumalate betweeen this terminals and will get dischagred thro doide. after discharging the remaining charge will...
HFN is done for other than clock net like reset nets,scan enables and some high fanout nets.
we need to HFN , actually we set a number , means more than this number treated as High fan out net .otherwise the high fanout net will see a lot of load and this net will c a large laod capacitance...
blocakge :
Placement block: to prevent standrd cells to sit there.. It wil block all standard cells including BUF and INV..
Non buf blockage: Block all standard cells to place where they have put blockage except BUF and INV..
Routin block: It wont alllow Routing Routing over those area.. M1...
Process means
Not my own words i got it somewhere dont mind
This variation accounts for deviations in the semiconductor fabrication process. Usually process variation is treated as a percentage variation in the performance calculation. Variations in the process parameters can be impurity...
Dear Anand,
While doping if the concentration goes more it leads to hot electron effect amd ion
degradation in deep sub micron cmos circuits which depends on applying voltage .
but there is term caled hot spots which has a particular defintion and it arises due to a certain problem.
I need...
Dear praneshcn,
Of course friend the buffers size will dramatically increase since what the gate count u obtanied is from front end. but to make the design properly
work without violations,to acheice timing there will be addition of buffers. this we term as backend.
Example...
Re: STA doubt
Dear vikas_lakhanpal27,
Multi cycle path must be configured during synthesis, to ensure
synthesis tool doesnot try to optimise the path into a single clk
cycle.
Multi cycle path needs timimg analyse its a need and must. it must be optimised
santu
cmos half adder
Dear VLSI technology,
U r asking how to draw a layout of half adder.
Fine u need a layout tool.
u need a transistor level(CMOS level) design of the half adder.
That cmos should be of certain technology.
Then it cmos level transistor should be designed properly like...
Re: DFM
Dear Vlsi Technology,
DFM is design for manfacturtibility.
I came into exist since 90nm technology was introduced
This was brought by foundry people since yeild and reliable was
important factors to them.
it is the phase in physical design flow where we check for possible...
Re: CMOS question?
Dear master piece engineer,
But i was told as it will be/ it has to be little more than that.
suppose if 90nm means we will be working on 1um.
sometimes double how far is this true and what is the actual thing?
also i was told during fabrication it may go down ie from 1um...
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