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Recent content by santhoshonkar

  1. S

    Programming ADS with Verilog-A

    Re: ADS with Verilog i tried with exact steps you have mentioned in the document but i ended up with the following status/error message, Warning detected by hpeesofsim during netlist flattening. Instance `X1': `b0' is not a valid parameter for an instance of `DCO'. Ignoring it...
  2. S

    How to add analog Verilog-A block in ADS

    Re: How to simulate Verilog-A in ADS Same here, stuck at the same step @kert could you please explain whats wrong
  3. S

    How to decide the width of core ring and power stripes?

    Hi there, Ametuer student here can some one help me out in finding answers to the following questions: -How to decide the width of core ring? -How to decide on the width of power stripes?
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