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Recent content by santhosh1626

  1. S

    What is the advantage/requirement of timescale in RTL design.

    What is the advantage/requirement of timescale in RTL design. Hi all, What is the advantage of timescale in design. In every RTL design we have `timescale 1 ps/1 ps or different values. What is the use and why it is required in design. Please reply me. Regards, Santhosh.
  2. S

    What is the difference between Store, Load and Move instructions in operation

    Hi !! I am working on the ARM processor. I have doubt on What is the difference between Store, Load and Move instructions in Processor assembly code. Thank you Regards, Santhosh Kumar
  3. S

    What is the advantage/requirement of timescale in RTL design.

    Hi all, What is the advantage of timescale in design. In every RTL design we have `timescale 1 ps/1 ps or different values. What is the use and why it is required in design. Please reply me. Regards, Santhosh.
  4. S

    What is the Diffrence between API and DPI.

    Hi all, I have a doubt on API. Where it will be use and how to in develop the API. We have any separate code or format for API. This API is developed ( Pre-defined functions/task) or user can develop ? What is the difference between API and DPI ? -- Regards, Santhosh.
  5. S

    Zero delay loop in verilog design

    # ** Error: (vsim-3601) Iteration limit reached at time 530 ns. # This is a zero-delay loop i am running the test case in UVM to verify the core. The core have accumulator,instruction decoder and ALU. The ALU is getting the first data only. While coming to second the instruction , the simulator...

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