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Recent content by sankudey

  1. S

    Switch-cap integrator noise simulation

    integrator noise Hi, Can any one help in doing in noise simulation of SC integrator - part of a incremental sigma-delta ADC? Any good reference or simulation type details will help a lot. Thanks Sanku
  2. S

    16b capacitor SAR ADC test result anayse

    Hey! Is this solved? It wil be interesting to know the updates. I had a small comment. Was there any digital calibration in place before and after the codes where between the coupling cap (series cap) appears? Any mismatch or top-plate to top-plate paracitics around the Cc (which can potentialy...
  3. S

    Sigma delta modulator (ADC) - material to begin with

    Hi Any one can give some quick reference / material to start with the sigma delta modulators (ADC) Thanks in Advance, Sankudey
  4. S

    How to measure DAC DNL & INL?

    how to calculate dnl in a dac? I guess you are asking for testing the DAC chip on board. there are several posts available in this forum regarding the testing of ADC/DAC. You can go through them. The first hand material will be the Handbook of Data Converters by Walt Kester (from ADI). This...
  5. S

    what the advantage of this compare??

    I feel - by sense you are correct, this is to increase gain. Actually, it is in +ve feed-back configuration and if you can break their latched state (which the previous post called as hysteresys), it will go to the other direction for any any error signal. This is what is required in comparator...
  6. S

    Looking for papers about CMOS Matching

    matching in multiple transistors pelgrom Following topic may be of your interest - - - sankudey
  7. S

    can anybody introduce a book about esd?

    Have you searched in the books forum - - sankudey
  8. S

    THD-cadence simulation

    fourier thd Any thing wrong with DFT? How does it differ by DFT (as you told 'roughly') and FOURIER? Aren't the algo's same? Any way, you do DFT on a waveform which is the output of the TRAN. I am really confused about the difference and their accuracy level. sankudey
  9. S

    THD-cadence simulation

    cadence thd I am not yet exposed to ic6.x. What is done 5.x is: do an DFT of the output waveform which will give you the frequency spectrum of the output waveform. From the frequency spectrum you will be able to find the amplitudes of fundamental, harmonics and other noise components. There...
  10. S

    How to do static and dynamic test for an ADC?

    Re: about adc test Just to add: A slow ramp is more preffered for static testing. Kester's "Data Converter handbook" is here in this board (in books section). There is dedicated chapter on testing. If you read, you can get to know the necessary things. luck!
  11. S

    Any good ref. for calibration of SAR ADC?

    sar adc thesis Its 16-bit I am starting up work on this - want ta have some good ref - like review paper or book on this--thesis also will do - I have already gone thru some initial study , like Razavi's., Maxim's site etc. Just to know if any thesis / book is known to you guys on SAR...
  12. S

    "analog layout automation"

    I have heard about VXL as well--- any way - that much could be automated, is an benefit, even if we cannot use it as it is. If it reduces some effort and time, its good.
  13. S

    THD reducing by using oversampling - is it possible?

    Re: THD THD should be related to distortion. This should not have relation with over sampling, as the distortion appears some where else , most probably be fore sampling. sankudey
  14. S

    Any good ref. for calibration of SAR ADC?

    sar adc thesis Any good reference / books for calibrartion techniques of SAR ADC? IEEE papers are OK. But if any comprehensive reference is known to anyone (may be book/ review paper / thesis etc.) would help much. Thanks in advance. Sankudey

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