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i have designed, a ASIC chip OF UART using verilog code as a input using .
BAUD RATE GENERATOR clock divide by dividing factor.
at post layout simulation on HSPICE (including parasitic capacitance and resistances after PEX analysis by Calibre tool in virtuoso) clock after dividing by 5 result...
i searched on net but i have not found any script which is used to fill dummy automatically in layout in virtuoso & calibre .
any body help me he know about script and link please send me
calibre antenna drc rule check warnings
these warning are coming during antenna rule check in calibre.
these warning are harmful or not.
how to remove these warnings.
warnings
ACUTE angle on layer M2 at location (64.11,0.99) in cell subil_pngatebuff_ESD122.
ACUTE angle on layer M2 at location...
Re: calibre antenna drc rule check warnings:
these warning are coming during antenna rule check in calibre.
these warning are harmful or not.
how to remove these warnings.
warnings
ACUTE angle on layer M2 at location (64.11,0.99) in cell subil_pngatebuff_ESD122.
ACUTE angle on layer M2 at...
I compared LAYOUT vs CLD netlist of UART design by RTL code and gds exported into Virtuoso.
There are no error but following warning is coming during PEX in calibre .
"The ground net "VSS/VSSO" defined in PEX NETLIST statement is not a valid GND net in the design."
what is the cause of this...
calibre pex warnings: port name on net not valid for netlisting; net id used instead
During LVS and PEX of UART layout to cdl netlist of UART in virtuoso some warning are coming.
There are no error in DRC , LVS and PEX...
it is not for all designs.
i do not like to misleading anyone.
i have share my own experience concerned with ASIC IC design.
I have designed a small design of UART in that initially i had not used RESET pin then in post synthesis simulation problem came as all outputs were stuck at undefined...
how to write testbench for "INPUT" pin in verilog
i have designed a verilog code for uart for that i need to use bidirectional data buses for that inout pin is used in verilog code but in test bench i dont know how to assign data to inout port and read data from inout port.
RESET pin is used to reset flip-flops in gate-level-netlist otherwise flip-flop goes in undefined state in ASIC ICs .
ENABLE is used to select chip, it is generally used by proper addressing of address buses to select IC.
how to add power pad in design .i already added I/O pad by adding pad in verilog-gate-level netlist generated from synthesis tool and back-end design on innovus(encounter) cadence cad tool.
in verilog netlist there is NO power supply pin .
How to add supply VDD, VSS pad in gate-level-verilog...
please explain type of OTA(folded cascode ,teliscop etc. ) design tool etc.
all transistor are biased in such a way that they must be in saturation state for all input/output voltage swing.
if you design folded cascode OTA input stage need large current to improve trans-conductance and output...
store data in registers to control mode of ic
A UART has been designed .
i want to control the baud rate using control pin CTR(1:0).
i want to store data in register permanent .
and use that data for control baud rate .
problem in synthesis some warning came
"initialization of registers...
if you add input/output delay constrain file (.sdc) or added input/output delay "attribute "then this problem may came.
remove all attributive then simulate and check results after that.
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