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I think to reflect SISO operation...
module siso(
input clk,reset,in,
output reg out );
reg [3:0]temp;
always @ (posedge clk)
begin
if (reset)
begin
out <= 0;
temp <= 0;
//in <= 1'b1; //just for testing make it "1"...
end
else
begin
temp <= {temp[2:0]...
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