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Re: SET UP TIME
thanks for reply...
if all semiconductor device has delay...then even.... and gate, or gate....should also have setup time.....then why is that only FF and latch is having a setup time....
rajkumar
SET UP TIME
hi everyone./...
i came with a very basic question....
why do FF require setup time.....if we consider a FF it would be a Master slave Latch....or a narrow pulse triggered Latch,.,,,,
so why do latch require a setup time...is it something related to Transitor parameter or gate...
RS-449 interface
hi ALL
A last try over here didn't got reply when posted on other groups so posting again the same topic here. I am hoping to get a reply
i need some help on RS-449 interface.I have an
instrument having RS-449 interface and want to
interface it with the PC
where can i get...
RS-449 interface...
hi ALL
didn't got reply when posted on DFT group so posting again the same topic here.
i need some help on RS-449 interface.I have an
instrument having RS-449 interface and want to
interface it with the pc..
where can i get the driver for RS-449.
what would be the best...
vhdl divide 1.5
hi
i tried to understand the PDF but couldnot follow it properly.i am not able to understand the effect of combinational loopback...
how to analyze the combination loopback circuit. any help would be greatful since i am not able to give much time towards it.
Re: does any one know where I can get DLL model for simulat
hi
i am not familiar with VCS simulator any way if u r palnning to use xilinx device then for simulating xilinx component they will provide unisim library..
search for unisim library, there u will find DLL component
Re: does any one know where I can get DLL model for simulat
hi
which tool u r using. if u r using xilinx ise tool, go to edit-> language templates..u will find the dll component given, include unisim librar
Re: How to avoid clk buffer
hi
The maaping of non-clock signal into bufg occurs depending on the load on the signal. If the load on the signal is high or if the bufg is free then the unwanted signal may get mapped into bufg,
either u should resctrict the usage of bufg by going to synthesis...
Re: FLI Help needed!!
hi
modelsim provides a very good FLI reference document along with tool
search in modeltech/doc/pdf/fli.pdf
u will get there if u don't get it i will upload here
hi
The reset pin is not locked in global input, so due to the load the reset gets duplicated.
now in cpci inteferace consider the bidirection data and tri-sate enable pin. after flattening the design these two FFs( output data and tristate en) are taking different asychronous reset because of...
Re: how to implement?
hi
in xilinx u can create ROM using coregen and initialize the value using coefficientt file (*.coe ) .
i have attached test.coe file u can check the fromat.
in Altera u can directly create memory iniliization file using GUI and megacore wizard
hope it helps
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