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So, if I find that .lib file with the time and power analysis information then I just include that into the library and it will work? Would I just analyze it to include it to the library or do I need to use another command?
I have a .sdf file that has timing information, but I think that the...
Right, I think whoever synthesized the circuit in Cadence used the .lib file, but I'm now trying to use this Cadence synthesized code with the Synopsys tools I have because I am unfamiliar with Cadence. The person provided the library in Verilog code so that the definitions of the modules that...
The reason I have to analyze the GSCLib_3.0.v file is because the uart_scan.v file that I have was synthesized in Cadence. All the library primitives that Cadence uses are in the GSCLib_3.0.v file. Using this file the normal (and, or, not, dff...) primitives that are used in the uart_scan.v file...
Hi,
In Synopsys DC I tried analyzing and elaborating two files I have like this:
analyze -f verilog lib/GSCLib_3.0.v
analyze -f verilog src-Trojan-free/uart_scan.v
elaborate uart
but I get the following warnings:
Information: Building the design 'udp_mux2'. (HDL-193)
Warning: Cannot find the...
Hi,
I am trying to generate test patterns for a finite state machine through Tetramax with and without a scan chain. I was able to do it after inserting the scan chain, but when I try to do it without the scan chain I get a warning when I perform the DRC.
The warning I get is: Warning: Rule...
The university that I am at has all the Synopsys tools like Tetramax, Design Compiler, and VCS. We don't have Mentor or ModelSim or anything. If it is not possible to do the mixed simulation with VCS then we may be able to purchase something else, but we would prefer to try to use the tools we...
Hi,
I normally work with Verilog, but I have a design and testbench in VHDL. Can anyone provide me with a script of how to simulate the VHDL code with Synopsys VCS?
Thank you!
Are you familiar with VCS? I tried analyzing both the files separately with vlogan and vhdlan and then compiling them with the vcs command, but it compiles the VHDL file like a Verilog file so I get a lot of errors. I also tried compiling them with the scs command instead, but I kept getting an...
Hi,
I have a design in Verilog and I used Tetramax to generate test patterns for it, but the version of Tetramax that I have can only write the testbench in VHDL and not Verilog. Does anyone know how I can run a simulation for my Verilog file using a VHDL testbench in VCS or some other Synopsys...
I have version E-2010.12-SP4. It also says that in the next version that comes out the VHDL option is going to become obsolete too.
Do you have a script for simulating VHDL files? I was thinking I could have the Design Compiler insert the scan using VHDL instead of Verilog and then I wouldn't...
So, I've found that I can only write the pattern file in binary, VHDL, STIL, and a few other things, but no verilog. If I were to write the pattern in VHDL would there be a way to use both my verilog design file and the VHDL test bench in VCS together?
I tried -format verilog_single_file but it still says that the command is ignored because it is obsolete. So I'm trying to simulate the pattern file generated without the -format verilog option, but when I type in the script you provided it says that both the stdlib.v and iolib.v library files...
Is there a way to get Tetramax to print out the input values used during fault simulation along with the flip flop and output values that are associated with each input pattern?
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