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Recent content by sameer_dlh25

  1. S

    what is different AXI and AXI3?

    AXI is gernel term used for protocol, It can be AXI3 or AXI4. Just search on ARM site. Hope this helped :) Cheers Sameer
  2. S

    refresh in DRAM and read or write

    NO it cannot. So this comes in performance path Cheers Sameer
  3. S

    Both Read,write trasactions parallel in AXI

    Hi Annasaikiran, As they are on independent channel they can execute in any order. Cheers Sameer.
  4. S

    Write response of axi

    Hi Vir_1602, "write response be always on next clock edge of Wlast signal or there can be delay between wlast and Write response." It is definitely possible have delay between WLAST and write response.Please note that if write response has to be given always in next cycle of WLAST then there...
  5. S

    [SOLVED] Can cadence NCsimulator initialize unresetable flip/flops?

    Hi George_P, I think you need some script. Unfortunately there is no easier way to do the same :-( Cheers Sameer
  6. S

    SPEF/SDF file for GLS

    I don't think NCSIM can read SPEF directly. SPEF is standard parasitic exchange format and does not contain delay value directly. Cheers Sameer
  7. S

    Why data tran violation is present?

    Re: Timing is clean yet data tran violation is there My opinion need to fix all clock and data path. One point is if transition is very close to lib range say max trans on data cell inside lib is 1 ns and you are at 1050 ps. In this case if timing path is met with decent margin [say 1 ns ]...
  8. S

    about low power flow

    I am not sure if conversion is seamless or 100% conversion is possible. The problem is both of these formats are concept wise little different, though most of the portion is similar :x Just check below discussion, though this is reverse UPF to CPF. I am not sure it will help...
  9. S

    ICC timing report -from clock

    Is this path is met with large timing margin ?
  10. S

    Disable OPT-1206 and OPT-1207 in Design Compiler

    I think look for 1. Check if compile_delete_unloaded_sequential_cells variable value. 2. set_dont_touch is applied properly. Let me know if this helps :) Cheers Sameer
  11. S

    Issue with .lib files

    Timing sign off is not accurate through such lib pins and can be risky. I think you should try to analyze why delays are non-monolithic.
  12. S

    Difference between increment and wrap burst types in axi

    Sun Ray, I gave example of 4 beat burst so actually 5th address can be anything means aligned or un-aligned as it is new transfer. The burst is aligned to the total size of the data to be transferred,that is, to ((size of each transfer in the burst) × (number of transfers in the burst)). In...
  13. S

    Checking 4k boundary crossing in AHB/AXI by an interconnect/bridge

    Yes interconnect checks same. I think the checking equation is added in AMBA 4 spec.
  14. S

    Difference between increment and wrap burst types in axi

    There is nothing special in AMBA. The wrap operation on AXI is same as other wrap operation. E.g. If we do 4 beat burst on 32 bit AXI with AxLEN = 16 and starting address 0x00000004 address Inc. Wrap ----------- -------------- --------------...
  15. S

    huge current problem by hsim

    quantized, I think this is because DC convergence was is crude. In this case dynamic simulation and delays are OK but current is quite large. I do not remember accurately but there is option to increase accuracy of DC convergense in HSIM.
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