Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by samankiamehr

  1. S

    tetramax path delay test

    I have the following code for path delay test generation: read_netlist s27_synthsized_scan_test.v read_netlist ../../Library/saed90nm.v -library run_build_model s27 set_delay -nopi_changes set_delay -nopo_measures set_delay -mask_nontarget_paths set_delay -common_launch_capture_clock...

Part and Inventory Search

Back
Top