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Maybe I'll find another interface that can, untill then i'm pretty much set. USB is pretty flexible so I can simply run it of the same clock, when dropping baudrate from 250.000 to 230.400.
The code I tried requires a down conversion to be at samplerate, so I was planning to use the page clock...
I gave up trying this, it has become a hassle. The clocks are too close together and the signal syncing frames is the only thing I have to cause a trigger from the slow domain to the fast domain. In triggering from slow to fast the problem just shifts, and has the effect of distortion shifting...
That's exactly the realization I'm having right now. I built the sample and hold to double flip flop. But it doesn't work because the clocks are mismatched to not even within an integer multiple of each other. I'm going to try and build the asynchronous FIFO, and soup up the clock so it's a...
That would be simplest. The concept is I can substitute errors in math which is about 80% in some cases, with altering the frequency which is to a lesser degree subject to reflecting these errors. If there's a way it would be really cool. Given I have USB ready and waiting makes there is another...
Finally I found my problem, it was in crossing clock domains. It goes from a higher to a lower frequency clock, and data should be present. So new to this I guess it's down to setup hold time for a given latch. I have 3 sepparate pll clocks, two of them should be at work, +1 later. Is this...
It's an occasional blip, it prefers the same spots though, always before or after the crest.
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Thanks for the advice, I will try that. Thought it would'nt be needed like this.
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Yes, it's in MHz, not in miliHertz. It can probably do a couple of decades...
Yes, it's in MHz, not in miliHertz. It can probably do a couple of decades tho. :grin:
I have the most basic constraint. I use sample and hold before the DAC and everything follows the clock scheme. It's not really critically timed.
derive_pll_clocks -create_base_clocks...
Hi,
I was doing some FPGA and was wondering if it's a problem on the FPGA side of things. The calculations are done using relatively high frequency and with a high data bandwith 64bit "large multipliers" and in the 20mHz range. I might have done something wrong with integer calculations..
My...
Thanks! So if I understand correctly. Altho faster, using block RAM would complicate things like a write readback per clock cycle due to having a databus?
I should convey these thins better :)
In case one there was a flat out times 36 nested if statement, with a times 6 latch. Using discrete...
In my case I think it's better not to have inferred memory, since "I read" my design should have multiple read/writebacks in one clock. And that is not possible with M10k memory? Does this mean I should stear clear of using arrays all together?
I found the option, it didn't auto initalize it tho. I guess I need to initialize the M10K thing manually for this to work?
Need to fix my code first..
I dont know, im relatively new about the ins and outs of verilog "I do get it's not driving serial logic all the time". The case was I had a relatively big array of latches (40x5 or so if statements), and in my mind it would be a tight little logic unit if I had an array supplying values to it...
Well it's not more efficient in synthesis anyway, so I went for the middle "goldylocks" zone in ease of coding vs serialism.
But I do think it's strange having to build a bus having a wire going to an array from a module. When you can just say, this array here.
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