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Recent content by sakti_boy

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    GSM modem/Microcontroller

    Hallo you can also use https://www.ftdichip.com/Products/Cables/USBTTLSerial.htm what you need to do, plug in the USB. it convert the data into TTL 5V for your microcontroller. Basically, the microcontroller can receive the data from those TTL signal (as an input data for your phone number)...
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    Very simple SPI Slave with VHDL (But have not worked)

    hi alan I am so sorry, make you confuse. It is my fault, I make mistake in copying the code. my original copy has so many comments to erase my previous trial of code, so i have to copy here one by one. Thus, some of it was not correct, but the main idea of program was fine I copy here again...
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    Very simple SPI Slave with VHDL (But have not worked)

    Hello, the problem is solved, :D I add another signal to tunnel the Input logic, I think it is because of my lack basic about vhdl. Heh ? I run the program with Quartus 2 12 sp1 web edition, it can be compiled. Thanks everyone.
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    Very simple SPI Slave with VHDL (But have not worked)

    Hi all, thanks for your help. :) I have already tried both of the cases. but it is still not working properly. each pins are still toggling high and low. the different is only the period, it toggles with very slow frequency, less than 10Hz (my SPI master send data 10kHz) However, this spi...
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    Very simple SPI Slave with VHDL (But have not worked)

    Hallo, I am quiet new with VHDL programming language. Now, I make an FPGA as SPI Slave, and microcontroller as SPI Master. This Picture is the SPI Master from the microcontroller (just normal SPI, without ChipSelect) Yellow is the MOSI (0x55) Blue is SCLK FPGA receive the signal from SCLK...
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    Verilog UART example program

    Hi Thank you very much for your help. Yes it is from fpga4fun.com, I try to run, and it works. I have a project to develop basic CAN and Flexray receiver and transmitter. Before I start to make those stuff, I start to learn more simple verilog programming to develop UART, SPI. Anyway, thanks...
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    Verilog UART example program

    Hello Guys, After several weeks, search and try to understand. I stuck to understand the following verilog program. reg [3:0] state; output TxD; wire TxD_ready = (state==0); reg muxbit; reg TxD; TxD <= (state<4) | (state[3] & muxbit); The program is to send UART Transmitter, on Quartus 2...

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