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Hi mail4idle2, thanks for your answer. I have doubt here, what about the 40 percent duty cycle? Do duty cycle don't have any impact on calculating logic delay
Hi guys a similar question was asked in recent test , can anyone please tell me how solve this question "A timing analysis shows that an ASIC has a clock skew of +/- 250ps. The flip flops used have a clock->Q delay of 120ps, an input setup time of 80ps, an input hold time of 375ps. The duty...
Hi all
I have compiled my code in Synopsys Design Compiler and calculated power using my Verilog code but I don't know how to calculate power of my code using Synopsys prime power(i.e using Test bench which is exact power). Can anyone plz tell me the process of calculating power using...
hi
I'm using sytem verilog to use two dimensional arrays in my program. when i compile for both testbench and for verilog code the compiler shows no error but in the waveform block the wave is not taking this two dimensional inputs and i'm not getting the output.can anyone explian me how to...
I'm designing a viterbi decoder for 3/4 rate convolution encoder. Can anyone can tell me how to design Branch Metric in it i.e complete architecture of BM
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