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hi guys,
counter_rst <= '0' when Breset='0' else '1';
process(Bclk,counter_rst)
begin
if(counter_rst='0')then --10bit counter
onekhz <= "0000000000";
elsif(Bclk'event and Bclk='1') then
if(onekhz <="1111100111") then --divide by 1000
onekhz <=...
hi guys,
I have some doubt about the vhdl code regarding the counters..
I need the sample code in vhdl for frequency division in the concept of asynchronous counters
I have a code but it's not working can anybody give a suggestion that what is a problem of it...
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