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Re: WHICH JOB < ASIC digital > IS SECURE & growing from following options ??
As verification consumes 70% of time for Designing an IC, verification Engineers have always more jobs than any any other positions.
To my knowledge, no of taps = no of coefficients needed. it also effects order of filter.
Also more no of taps => high precision, more hardware, more computations.
1) you will get to know BW of LTE only after detecting PSS & SSS. once you detect PSS&SSS, you are downlink synchronized & you can read PBCH to know LTE BW.
2) PSS is always mapped to central 6RB's irrespective of LTE BW. so you always need to extract central 1.08MHz BW and do correlation with...
hello all,
i want to implement 16qam modulator on ALTERA STRATIX II FPGA. i am getting input data serially one bit at a time. for 16qam, i need to take 4 bits at a time. these 4 bits serves as address for my LUT to get I and Q values. then i will multiply I and Q values with orthogonal signals...
as far i know using (0<=EEPROM_Read(0x21)<=29)) won't work correctly. instead use ((EEPROM_Read(0x21)>=0) && ((EEPROM_Read(0x21)<=29) to get expected output.
next as betwixt said, assign (EEPROM_Read(0x21) and (EEPROM_Read(0x22) to variables at the start of code to speed up your design.
i am working in VCS for my project. i need to check simulation output for many modules. suppose if i am simulating module2 and if i want to check simulation output for module1 (which was previously simulated), currently i am simulating module1 again and seeing result. this is definitely waste of...
i am not using UPF. i am using Synopsys Design Compiler to insert RTL level clock gating using "insert clock_gating" command
---------- Post added at 09:57 ---------- Previous post was at 09:56 ----------
hold violations at the input of FFs
hi
i'm using RTL level clock gating in my design for reducing power consumption.
i'm taking everything ideal(setup time=0, hold time=0)
after inserting clock gating and after synthesis, i'm getting large hold time violations.
help me how to solve this
thank you
Hi all if u worked on prime power please read and help me.
When i am calculating power for a module which has some submodules inside, it is telling unable to resolve references & creating black boxes. I am using the following script for calculating power
set search_path "."
set link_path "*...
if anyone worked on prime power can help me please. i read my netlist file and libraries. my verilog code contains submodules. after i gave link command it is telling unable to resolve references to submodules. without submodules i am getting power consumption result but with submodules in...
can anyone help me please
in primepower after giving link command, it is telling unresolved references and creating black boxes. what to do to solve this problem?
thank you
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