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Recent content by safwatonline

  1. safwatonline

    difficult fundamental question: about delta sigma modulator

    i don't get this equation: v1(n) = v1(n-1) + 1*(x(n-1) - y(n-1)) + ff(n-1)
  2. safwatonline

    voltage change at node, modelling leakage path

    Re: voltage change at node? To solve this, calculate the transfer function in s-domain. then apply a unit step from 0 to Vdd denoting initial charging then use final value theorem to calculate the final value. this will give u the zero stated by stefannm. :D
  3. safwatonline

    very low noise Bandgap reference

    low noise bandgap reference usually chopping requires a filter to remove the ripples
  4. safwatonline

    quote of the day - inspiring and funny quotes

    quote of the day.. there are 10 types of people; people who know digital and others who don't
  5. safwatonline

    If you need help with ESD... ask me in this post

    How about adding resistors, i know a couple of designs that can be quit intolerable to ESD resistance (even few Ohms) Can the IC survive if it depends solely on the Diodes?
  6. safwatonline

    How to do Verilog-A modeling in OrCad

    orcad verilog-a i dont think verliogA works on Orcad
  7. safwatonline

    Delta sigma modulation using verilogA (and Cadence)

    veriloga sigma delta code I am not sure but i thought there might be some error in the FFT as the plot of the blue spectrum shows not that pure sine-wave, specially near the signal (or maybe my eye is just fooling me)
  8. safwatonline

    somebody please get me this pipelined adc thesis.

    thesis + adc attached!
  9. safwatonline

    Delta sigma modulation using verilogA (and Cadence)

    verilog a what is the snr of the input
  10. safwatonline

    Problem with PLL which does not lock

    pll ns locking i would say check the VCO
  11. safwatonline

    Low SFDR of SHA at nyquist input

    may be the sampling switch charge injection
  12. safwatonline

    [SOLVED] creating calibre view

    calibre view port this file is automatically generated. it is function is to map the pins of the symbols of cadence design kit to the ins generated by calibre
  13. safwatonline

    a question about quantization noise

    for a busy signal with large number of quantization levels the signal can be considered white. why DC to fs/2 because it is sampled signal with sampling frequency fs
  14. safwatonline

    Time/Phase measurement circuit

    Time/Phase measurement well, maybe a PD followed by a time to digital converter (Counter for instance)
  15. safwatonline

    Time/Phase measurement circuit

    high speed analog phase measurement circuit phase detector followed by Charge pump
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