Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
solder void
hi..
does anyone know and have experience with LGA (Land Grid Array)?
i would like to know how if i want to reduce the solder void issue.
as far as i know for BGA the max solder void % is 25%. but for LGA, there is no spec yet in IPC.
how the PCB design, stencil opening, solder...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
