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I find it's very difficult to compromise between hysteresis voltage and delay time when we want the hysteresis voltage is larger than 400mV from the basic hysteresis comparator structure.
For example, I can ensure the 500mV hyrsteresis voltage, but the delay time is huge [about tens of us]...
I think, the reason is that you place the input ac voltage source on no-invert input of opamp to get phase decrease from 0.
you can get phase decrease from 180/-180 if you place the input ac voltage source on invert input of opamp.
Added after 8 minutes:
Sorry, what I say is for the case...
hspice average current meas
Maybe you can place a ideal voltage source in the line of vdd, all current must flow cross the line. Set the ideal voltage source value=0 and you can get the whole current of the circuit. Then, you use the function power=vdd*I(total).
This method is not very simple...
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