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Recent content by S0933263236

  1. S

    Im looking for arm7 model for simulation.

    :) Hi , the_penetrator : I need a verilog ARM-7 core as a reference. Can you email me a copy too ? Thanks !
  2. S

    register or latch compare with memory?

    1. .db file for Design Compiler => binary file format for cell libary or design database. (Design compiler is a digital-only tool) 2. .v file => means Verilog file normally , it can be : (1) verilog simulation model (2) synthsizable design file...
  3. S

    register or latch compare with memory?

    area compare (use the no. of MOS FET) : 1. sram memory cell (1 bit) for embeded sram logic process => 6 MOS FETs 2. for UMC 0.5um GlobeCAD standcell library : RL_DFFRBP(D Flip-Flop with Asyn. /Reset) => 30 MOS FETs RL_DLHRBN(D Latch Active High With /Reset) => 20 MOS...
  4. S

    Which StandCell Library include Integrated gate-clock cell ?

    Thanks ! I did know that DC with power compiler feature can handle gate clock circuit without integrated gate-clock cell in standard-cell library. And, I did know how to implement the Gate clock funtion(using VHDL/Verilog) with DC (no power compiler feature). For some reason , I still want to...
  5. S

    Which StandCell Library include Integrated gate-clock cell ?

    Synopsys Power Compiler can use integrated gate-clock cell (Latch type) to implement a low power design. Which StandCell Library support the integrated gate-clock cell (Latch Type) that can be used by power compiler ?
  6. S

    Already have FPGA compiler, why need Design Compiler (DC)?

    Design-Compiler with FPGA library can do FPGA synthesis. But the Quality of Result (QoR) is not good. For ASIC (cell-base) DC and Incentia can do good job . For FPGA , the first choice is Synplify Pro . :D
  7. S

    How to deal with high-fanout nets using DC

    typical fanout for clock synthesis The clock-tree synthesis/optimize tool "clockwise" from Celestry can synthsize not only clock-tree but also high fanout net (ie. Reset net). :D

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