Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
toggle rate analysis
Dear vlsi_eda_guy,
In reference to pwr estimation of a design by annotating only static probability and not toggle rate as part of switching activity annotation,
If we annotate the switching activity with only static probability by using the following cmd...
detach scan chain
Hi,
I have a design in which I find there are several scan chains existing. Thus, there is no one single scan chain in the design.
Is there a way that I can detach these several existing scan chains.
Is it possible with DFT compiler.
Thx
Nikhil
Hi,
I am using design compiler to estimate the power of a design. Switching activity is annotated by setting only the static probability value on all primary inputs and leaving design compiler to compute the toggle rate to itself. Is this the right way to estimate pwr of a design.
What is...
Hi,
When I try to read in the saif file into design compiler, which is created from the vcd file generated from rtl simulation in modelsim, I am getting the following error:
Error: No switching activity has been annotated. (PWR-362)
Warning: There are 711 objects not found during annotation...
Hi,
Can anyone help me regarding this
vcd2saif -i myfile.vcd -o bsaif
VCD to SAIF translator. v2.1. Synopsys, Inc.
direct mapping all VCD instances
processing header of VCD file: /work_local/softjin/dft/pavan/power/pwr_estimation/sept18/myfile.vcd
(continuing)1: unexpected command: $date...
Hi,
I need to do power estimation of a gate level netlist.
I am trying to read in rtl of the same gate level netlist and test bench into modelsim and perform simulation. I want to write the output in VCD format which can be converted to SAIF format. The saif file can be read into DC and then...
Hi,
I know that layer hopping can be used as a way to fix antenna violation, but does this mean that by only moving from lower metal layer to top metal layer antenna violations can be fixed or can it be even done by moving from top metal layers to bottom metal layers.
Thx
S.Nikhil
Hi,
What are the factors that determine the setup time of a flip-flop.
According to me, it is the input transition and slew.
Let me know If I am correct.
thx
S. Nikhil
Hi,
What is an via array. Explain its usage during power routing and the impact on power routing.
How to decide the number of vias in an via array.
How is an via array represented in a LEF. Can we add custom via arrays to the LEF file.
Does the addition of via array reduce the...
driving strength of gate
By upsizing a cell ( increasing the drive strength), we are actually increasing the width of the diffusion thereby getting less delay. Thus, with less delay the gate can drive the signal more efficiently.
thx
S.Nikhil
Spare cells like nand, nor gates are spread over the entire chip in p&r. At the final stages of the design, we find that some gates are not working appropriately or if we need to add extra logic to the design, we can make use of these spare cells by connecting them as requd to derive the reqd...
Re: what is cross talk ?.when will it is come?how to reduce
Crosstalk is the unintended signal distortion due to coupling capacitance between two neighbouring nets.
Due to decreasing process nodes to cope with the requirment of routing, additional metal layers are being used. The width of...
synopsys
Hi vlsi_eda_guy,
Thx for ur valuable information. It is indeed D8 violation at the pre dft drc stage and I did use set_dft_configuration fix_reset enable cmd as part of the autofix.
Moreover, when I did observe the fanout of the reset, it indeed is getting gated in the design.
Now...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
