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synthesis keep
I have a clock generator in my design, composed of some cascaded inverters. However, during synthesis the tool deleted/ignored most of the inverters making an incorrect hardware implementation. Any RC script command to preserve the clock generator module ? TIA
I've synthesized my design using RTL Compiler. However, I observed that the generated SDF file contains only the worst/max delay for any gate. The minimum and typical delay values are missing. Is there any RC script command that will fill up the missing delays during SDF generation? TIA
I have a vhdl code, with constant values tied at the ports
e.g. m1 : port map mux ('0',a,b,c) ...
i've got errors because of the constants direct port assignments
Any additional script commands to remove this error ? TIA
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