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When I imported the VHDL file to my new project i tried to synthesis it with xilinix 12.3 and it did with a few warnings. Then i tried to implement the design and it stopped in the mapping. With the following errors:
ERROR:Map:116 - The design is empty. No processing will be done...
Hi!
I generated an Floating Point adder/subtracter using Core Generator and imprted the vhdl file in my project. The vhdl file imported was succesfully synthesised by it wasnt implementable. Why is this? and to simulate this in ModelSIM i have to import some new libraries? Help
THANKS...
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