Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by rx78nt1alex

  1. R

    VHDL sram testbench problem..

    THANKS vipinlal so much !!~ Finally, i completed the simulation, and i found i made some careless mistake , so that i could not simulate before. Thanks again!!!!~
  2. R

    VHDL sram testbench problem..

    thanks vipinlal the blog is very useful! I'm now still finding the problem. i changed my program below, but it generated some error... i uploaled the image below.. Thanks again... library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use...
  3. R

    VHDL sram testbench problem..

    hi, devas i used this statment to replace the positional association, but the complier is still warning me "Types do not match for port addr", do you have another idea.... thank you so much! DUT: SRAM1 port map (clk=>clk_i, cen=>cen_i, wen=>wen_i, addr=>addr_i, din=>din_i...
  4. R

    VHDL sram testbench problem..

    I'm writing a testbench for sram, but i found the port map type in my testbench which does not match to the sram.vhd, i have no idea how to rectify it. Below are the sram design and my testbench design. Could anyone give me some tips how to rectify my testbench in order to test the sram.vhd...
See more

Part and Inventory Search

Back
Top