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Hi Frankrose, here is a pdf explaining strong arm latch: https://www.seas.ucla.edu/brweb/papers/Journals/BR_Magzine4.pdf
the timing of the output data rising edge of a flip flop will vary depending on circuit noise, so was wondering how to characterize this noise..
Or is flip flop noisy at all? would you simluate its noise as you would do with a strong arm comparator? Why is strong arm comparator noisy but not a flip flop?
Hi all,
Wondering if any of you knows whether there is a manual that has the solutions for Razavi's cmos analog design book problems?
Google answers were misleading...
Thanks,
Ok. I don't seem to have this kind of problems right now, like ringing and oscillations (like you mentionned, i believe this is one benefit of my large capacitors...). Thanks a lot for your answers Prestonee.
Hi! Yes if i change the clock period i got less problems...So yes it is the values of Ron...But mostly the fact that i put around the amplifier simple nmos switches....Caus they were connected to an integrating output and their Ron changes depending on that....So i used transmission gates in the...
Ok. Changing the values of Ron makes the circuit behave in weird ways, in different ways...
Would that mean the circuit is just dead ? i mean if no value of Ron satisfies the desired transfer function, then i will have to find a way to remove the switches from around the amplifier ? Can i prove...
Hello again!
Everything was working perfectly when i was simulating the real amplifier with ideal switches (the offset cancellation scheme was working, as well as the integration),
When i replaced the ideal switches with real ones (mos switches) the amplifier did not seem to like them....Does...
Hello all,
My question is about the considerations of sizing the switches in the integrator of the attached photo with respect to the values of capacitors C1 and C2:
The switches marked as S1 (those of the first phase) should be different in size with respect to the switches of the second phase...
Ok. Thanks a lot Prestonee for all your answers. I think that the timing of the switches is good now, as well as the az configuration...but i still don't have the result i want and now i understand that i have another problem that i have to deal with (Well on this one i think i will have to fly...
Prestonee, you are right, the problem is apparently with the timing...initially i only made p1 and p2 non-overlapping, and then when i created a p2q and p1q the amplifier started integrating around the common mode but it saturates at a certain level....I made the delay longer to check if it will...
Prestonne,
Please find attached the schematic i am using for autozero: during phase1 I sample the input capacitors and the auto zero capacitors, and during phase 2 i integrate by connecting the feedback capacitor "after" the auto zero capacitor so that the amplifier's offset is canceled. My...
Hello Again!
I implemented the auto zero scheme first using an ideal amplifier.......it worked with the ideal amplifier,
But when i replaced the ideal amplifier with a real one, the obtained results were weird: If i connect the amplifier as follower during the first phase i obtain outputs that...
Ok now i think i understand the concept of double integrate to eliminate offset...but does this hold for a fully differential amplifier too, which have 2 outputs ?
Ok Now i understand the auto zero approach thanks.
Can you give me a reference where i can understand the approach of ping ponging the inputs and doing a double integrate ? From your explanation it seems to me that it will be more interesting, you said that it's the common mode for chopping...I...
Crutschow, this is intended for a Built-In-Self-Test applications
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BradtheRad, the pulses are fixed lenght, and there might be an irregular mix of highs and lows
My supply voltage is 2.5Volts, and using only one transistor as current source will produce a nonlinear signal...
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