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Recent content by rsqf

  1. R

    synopsys design constraint

    It seems like that your SDC file 5th line has a strange port which could not match your design.
  2. R

    clock multiplexer problem - help needed

    Re: clock multiplexer Yep, you could use the case analysis for safety
  3. R

    clock multiplexer problem - help needed

    Re: clock multiplexer You could use the max frequency(in your design) clock to synthesis.
  4. R

    Multi voltage and multi power mode design partitioning

    And I have a question : Do you want to create two seperated power domain, and there is a module named "A", in one power domain, and another module named "B" which is the same as module A, in the other domain? If the description is correct, I think you need not to rewrite the RTL code.
  5. R

    help me, the error of astro

    You can search the index of error MWNL-032. The tools should have some description.
  6. R

    Abt clkbuffers and clkinvs

    In my opinion, you can use invclk instead of the bufclk in the palce where the transition time does not have much margin.
  7. R

    Abt clkbuffers and clkinvs

    In my opinion, if you use invclk instead of bufclk, the clock tree will be so long because of the fanout of clock. So the tool will decide place where use inv or buff.
  8. R

    Constraint on Multi-Clock with a same source

    You could use this command: set_clock_group {} It defines the group of clock . The detail information you can find in the DC ref doc.
  9. R

    Constraint on Multi-Clock with a same source

    If you can confirm that the clkA and clkB ablosutely come from the same source, and according to the design requirement you do want to check the timing between these domain, you can set these clocks in the same clock group. Then tools will check timing in these domains.
  10. R

    Abt clkbuffers and clkinvs

    These issues are considered in the ClockTreeSynthesis phase. Are you in this phase?
  11. R

    Constraint on Multi-Clock with a same source

    yep , you could set the generate-clock using the same source clock. Then the STA tools will calculate the setup/hold time in these clock domains.
  12. R

    How to use a library without scan cell to insert scan chain?

    Yep U could find the scan-DFF description in the library doc.
  13. R

    how to specify internal net as scanmode signal

    I am sure that there is a command u can use. U mean the signal is generated by the other logic and control the whole chip to into scanmode? I think u could set the signal to 111 (than the chip will be set in the scan mode). the command will be set_dft_signal -constant or test_hold something...
  14. R

    DC Problem : Module contains unmapped components

    dc unmapped Tools will check and use the library which you set to mapped the instance , if there is no correct library, the tool will left the internal component in the netlist. If your lib set is correct, you can check which module called the MOD_UNS_OP, and how it works in the RTL code.
  15. R

    DC Problem : Module contains unmapped components

    select_op synopsys library please check your link and other library when using DC compiler, the unmapped cell should not exist in the netlist.
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