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Recent content by rsabhilash

  1. R

    Cross probing in Allegro 16.5

    Hi all, I am a newbie in PCB design and apologize me, if my question is a simple one. I have a design of a board. The layout is available in .brd format and schematic is available in .pdf format. I would like to alter the board . My question is that, after making schematic from the available...
  2. R

    ISE simulator v/s Modelsim

    Ya,I think so.Now I started the simulation of tri_mode_eth_mac (IP core from XIlinx)
  3. R

    ISE simulator v/s Modelsim

    Now data is available at output while I make rd_en high.
  4. R

    ISE simulator v/s Modelsim

    I checked it.When data written became greater than it's depth then full flags goes high. On reading one data from the full fifo the full flag goes low.
  5. R

    ISE simulator v/s Modelsim

    That's old waveform.Now empty flag goes low
  6. R

    ISE simulator v/s Modelsim

    hello, It's working well.Now I can watch internal signals.
  7. R

    ISE simulator v/s Modelsim

    The command "add wave -r /* " does not work for ISIM. But in the tab Sim objects all the internal signals are preset and can be added to the waveform window by just drag & drop.
  8. R

    ISE simulator v/s Modelsim

    Actually there was a problem in my code. We have to wait 100 ns for global reset to finish.The stimulus are supplied after 100ns.But I fired them before 100ns.When I delayed the stimulus by 100ns there was data in dout. Wrapper file fifo.v is sufficient for simulation in ISIM . Thanks for your help
  9. R

    ISE simulator v/s Modelsim

    @vipinlal I didn't add fifo.xco file to the project. Is it possible to view internal signal of IP core.How ?
  10. R

    ISE simulator v/s Modelsim

    I think, for write operation just make wr_en=1 and din=data. Is there any thing that I might have forgotten ?
  11. R

    ISE simulator v/s Modelsim

    Here I am giving the program My top module is tx_fifo.v tx_fifo.v module tx_fifo(din,wr_en,wr_clk,dout,rd_en,rd_clk,full,empty,rst ); input [7:0] din ; input wr_en ; input wr_clk ; input rst ; input rd_en ; input rd_clk ; output...
  12. R

    ISE simulator v/s Modelsim

    Hello, The dout is zero,they are not unknowns.
  13. R

    ISE simulator v/s Modelsim

    I didn't get any data in dout.
  14. R

    ISE simulator v/s Modelsim

    Test bench is given below module fifo_test; // Inputs reg rd_en; reg wr_en; reg wr_clk; reg rst; reg rd_clk; reg [7] din; integer i = 0 ; reg [8] stim[31] ; // Outputs wire full; wire empty; wire [7] dout; // Instantiate the Unit Under Test (UUT) fifo uut ( .rd_en(rd_en)...
  15. R

    ISE simulator v/s Modelsim

    Thanks for your immediate reply. I am trying to simulate IP fifo generator in Xilinx ISE. But it is not working.I can't read the data from fifo by pulling rd_en up. What will be the problem
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