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Hi! Thank you for your quick reply. Understood; nothing will be configurable.
The 4 outputs ( when 4 is selected instead of 2) are going to 4 different CRC engines in parallel so I can get their CRCs in the same clock. In case of of 2 chunks of MD; say MD1 and MD4; only these two need to be...
Hi I wanted to know how I will represent this code in hardware. I will explain it with a picture.
I have 8 different inputs to select from. In one clock, I will either choose 4 chunks of it or 2 chunks of it.
I implemented the harware to pick the first 4 inputs and then to pick 2 inputs out of...
Hello
I want to implement a fully parameterized multiplexer. The minimum inputs that it has is 2. Both of them are 16 bit.
What needs to be configurable is the additional number of inputs that can come to the MUX and also, these are all of different widths. I get that the output width of the...
There was no confusion actually. there are a lot of things that have to be taken care of in this one module. I am sorry about that. This thread helped me resolve the two main scenarios of variable width input as well as 2 different CRC polynomial.
The `ifdef is for a completely different...
So what I am dealing with is a lot more convoluted. What you said is working for me when I am choosing between different widths and polynomials. I just use case. So all the hardware is present.
But I have this additional action where a few number of bits are getting added to my data and coming...
Re: Variable Width CRC generator based on parameter "crc_poly"
Yes you are right. I thought there was some way for me to avoid the amount of logic that is needed but I guess I will any way need those many MUXs and DEMUXs.
Thanks for your help!
Re: Variable Width CRC generator based on parameter "crc_poly"
The polynomial can be parameterized because I can choose which CRC I wish to implement. But the input data width cannot be parameterized because it comes in along with the select signal and based on the select...
Re: Variable Width CRC generator based on parameter "crc_poly"
Hi!
That works for the output when I am choosing which polynomial width I will be using. It can be parameterized then. But when I am thinking about the inputs coming in (which are of different widths), these inputs depend...
Hi! I want to make a general module for CRC generation for different widths of data input and also using 2 different polynomials that happen to be of two different widths.
For choosing the input width, there is a select signal as well.
I tried implementing this by making use of case and...
I wish to make a parameterized CRC generator that takes different widths of data in and gives 2 different types of CRC at the output. This depends on the parameter "crc_poly" which will decide whether the output CRC will be 32 bit or 64 bit.
My code will have all the different combinations of...
I tried an FSM implementation but the two operations seem to never work together. Getting new data in every clock and appending the next bit of the append_data are not getting synchronized.
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Hi,
No what i drew was only an example.
Basically in 1st clock, 1st stream of...
Hi,
the two are related but they are not the same issue. One issue is about connecting the modules and another is about whats going on inside the module.
But if you say what I mentioned above about the MUX and DEMUX is correct, then I wont try any harder to come up with a better...
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