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Recent content by RonaldSill

  1. R

    cadence assura DRC error

    Looks to me like you need at least 0.03 overlap of PP past the diffusion edge. PP probably being P-Plus
  2. R

    setting the grid sacing in cadence

    Minimum manufacturer grid is set by the process being used. This is the minimum grid snap that particular process can build to. This minimum grid size should be set in the tech file of that particular process. If you have a tech file that is reliable, usually part of a PDK from the fab, then you...
  3. R

    Change in TSMC 065 DFM rules?

    Looking for those who use this (tsmc 065 dfm rules) what do you desgin to for metal 2 for example. Our DFM check used to be .18 width and space... now it's .13 space and .1 width. Our DA group looked into it but swears it was never .18. We've been using and checking to .18 for years... it just...

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