Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by roli

  1. roli

    Laser CNC plotter by DaKKi

    Cute idea ! Tell us more about it: Jog speed, accuracy, material type to scribe on, ...etc Thanks !
  2. roli

    how to generate WGL format file ?

    Message is unavailable.
  3. roli

    HOW to transfer VCD to WGL format

    Message is unavailable.
  4. roli

    how to specify internal net as scanmode signal

    Yes , assuming you define precisely (in DFTAdvisor) the exact combinatorial equation of "dft_tst<2:0>" which produces 'scanmode'.
  5. roli

    how to specify internal net as scanmode signal

    Yes you can, only if the Tester (and DFTAdvisor) can fully access (via Primary Inputs) & control the combinatorial logic which outputs the internal 'scanmode' signal.
  6. roli

    VCD vectors to WGL (tester) format conversion - here's how !

    VCD vectors to WGL (tester) format conversion After digging into Mentor's "FlexTest" I managed to do it, here's the flow: [ all "//" delimiters are notes delimiters ... ] 1. Edit a VCD read control file ("vcd_control.scr"). In my case, a 500nS test cycle, it looks something like this (note...
  7. roli

    Why PLL is used instead of DLL for DDR?

    PLL vs. DLL for DDR Please, first explain the differences (and trade-offs) between PLL & DLL, especially in terms of practical implementations in full customed CMOS process.
  8. roli

    TSMC Launches First Interoperable Process Design Kit (iPDK)

    https://blog.taragana.com/pr/tsmc-launches-first-advanced-technology-interoperable-process-design-kit-4275/ [ For the time being - for 65nm. I guess next will follow ]
  9. roli

    Problems with opening IC610 documents on Fedora 7

    problems with ic610 The order of your own defined $LD_LIBRARY_PATH variable doesn't matter, because whatever you set it to, 'cdsdoc' [which is the script invoked by the IC6.1 Help menu] sets it so: LD_LIBRARY_PATH="$INST_DIR/tools/lib:$LD_LIBRARY_PATH" such that the Cadence Install...
  10. roli

    Failed to start cdsdoc, please help !!!

    Thanks Rookie, Done exactly what you've advised, and resolved the libgcc error ! but now I get a new error: =================== 12:56pm [centos]> cdsdoc [1] 11090 12:56pm [centos]> CDSDoc, version 2.1 Copyright © 2000-2003, Cadence Design Systems, Inc. Starting browser ... *** NSPlugin Viewer...
  11. roli

    guide for installation of IC5141 USR5 on RHEL 5.1

    Thanks 'hock' - you've done a great job !
  12. roli

    Calibre set-up in Linux/ No network card

    You must give your HOSTID to Mentor in-order to issue a valid license for you. [ after installation, your HOSTID can be retrieved with the Linux command 'lmhostid' ]
  13. roli

    Clock Uncertainty/Skew

    No, the above commands ('set_clock_latecy') emulate the clock tree NET delays (Min./Max.), and NOT jitter.
  14. roli

    VCD vectors to WGL (tester) format conversion - here's how !

    I need some experienced hints as to how generate WGL formatted vectors from VCD vectors (that latter was generated from a functional NC-Sim simulation) ? Notes: 1. I have acces to both Synopsys 'TetraMax' and Mentor DFTAdvisor (+FastScan), but have no practical experience with neither tool. 2...
  15. roli

    PADS default library in Excel format

    library excel format It is free but you have to register with a Business email. Is there a direct link to download ?
See more

Part and Inventory Search

Back
Top