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Hi erikl,
Thank you for showing me an alternative way. I've tried to running it. I did manage to sweep the load current.However, i am facing a problem where i cant sweep the W of the pass transistor. It keeps having this error where it doesn't recognise my pass transistor.=( I'm not sure why. I...
Hi dick_freebird,
Just for clarification, so did the method i used to get Id vs Vds curve acceptable?
While it appears to be upside down,hmm.... i still think it is wrong.
Because the Id axis value doesnt come close to the value i've checked through DCOP of pass FET.
Well since it is a PMOS...
Hi,
I want to simulate an I-V curve wrt to different sizes of my PMOS pass transistor to see its functionality. But i am not sure whether i am even doing the correct way.
So from the figure, in order to get Id vs Vds curve, I gave two DC source,VGS of 0.5V and VDS of 0.3V (located near the...
Hmm...if this is cause by "noise", then shouldn't my post-simulation result be distorted too?instead, my post-simulation results are much much better.
i've attached my post-simulation result for your reference.
The 'M' stands for milli.
Initially, i disregarded the distorted output shape as it is insignificant in my opinion, but my lecturer insisted i explain the cause of the output spikes/distortions.
What is simulation artefact?
Hi everyone,
Attached above is the transient result of my LDO with output of 0.9V. The first figure is at 0oC, the second is at 27oC and the third is 85oC.
For 1st figure, the output is very distorted.
For 2nd figure, the is a sudden glitch at the front.
For 3rd figure, the output is going...
I will try my best to make it clear.
I have constructed a LDO regulator testbench to test my AC results such as the phase margin, gain margin and the power supply ratio(PSR).
This is my pre-simulation results and i got the results as it should be.
Then, i proceeded to layout. After passing DRC...
Hi all,
I hacked my PEX netlist to get post simulation results for my LDO regulator.The post simulation for my AC(gain margin n phase margin) did change as expected(different from my pre-simulation results) but my PSR results for my post-simulation is the same as my pre-simulation result. It is...
Opps, it appears my pics were not uploaded properly at my mentor graphics lab.I will reupload it tomorrow since the pics is not with me currently.
Sorry for the inconvenience.=(
Will get back to you.
Hi everyone,
I did my LVS and i got this missing net and missing instance errors.I've look at it so many times but i cant seem to figure out the cause of both problem.Please help.
Thanks
I suppose it is quite impossible to design this circuit with a supply of 1.2V. Is there an alternative to implement this VCCS with such a low supply?How about if i were to implement self-biased cascode?
@leo_o2:Hi, even if i were to use a PMOS instead of a NMOS, will there be a significant...
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