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Recent content by rohit khandelwal

  1. R

    regardin threshold voltage libraries

    hello, i m using austria microsystems support foundry for my thesis. i have to use different threshold voltage libraries in my project. there are various libraries in this ams support like "corelib", "functional" etc. from where i can instantiate the instances but i m unable to find out...
  2. R

    regarding cadence spectre simulator

    can we calculate leakage power thru cadence spectre simulator. if yes, then how , please help me i am in urgent need of this. i will be very thankful to you.
  3. R

    to get hvt transistor in cadence virtuoso

    how i can be able to invoke a high thrshold transistor in a cadence virtuoso/spectre suite. i am using ams hitkit 0.35u support. please help me.
  4. R

    regarding threshold voltage of a particular technology

    i am using hitkit ams 0.35u foundry support in cadence. so, if i am taking a mosfet from library then how can i find that mosfet's threshold voltage. please help me thanks in advance
  5. R

    need help in cadence virtuoso spectre

    how to calculate power(dynamic and leakage) in cadence virtuoso/spectre design flow.
  6. R

    need help in cadence virtuoso spectre

    i have to calculate power of the circuit how can i do it in cadence virtuoso spectre design flow. and how i can calculate leakage power in cadence.
  7. R

    need help in cadencevirtuoso/ spectre.

    plz someone help me in calclating power in cadence virtuoso spectre design flow.
  8. R

    need help in cadencevirtuoso/ spectre.

    how to calculate power(dynamic and leakage) in cadence virtuoso/spectre design flow. first i made a schematic of an inverter and then did its transient simultion and when i did the simulation by appending a capacitor at the output then the simulayion gave totally wrong characteristic. plz help...
  9. R

    Low-power design lessons and reference

    Re: Low-power design paper on mtcmos, one of the mostimp technique of low power vlsi
  10. R

    vhdl and verilog related

    good books and some pdfs
  11. R

    What is the setup and hold time?

    setup time * hold time Setup time is defined as the minimum amount of time BEFORE the clock’s active edge by which the data must be stable for it to be latched correctly. Any violation in this minimum required time causes incorrect data to be captured and is known as setup violation. Hold time...

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