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This was a really helpful response.
Although, it only works if i use #2 for reset and repeat(1) @(posedge clock) fro every data stimulus. And gives me the desired waveform.
Hello,
I am writing a testbench in which I am giving the inputs to my module. These inputs include a clock, reset , data and shift_data value that go to my DUT.
I am trying to make use of
always begin
#1 clock = ~clock;
end
initial begin
reset = 1'b0; //its a negedge triggered block...
I understand. This works as there are only 2 cases. But if i have more than two cases, I will have to use "CASE" which requires its own always block like
always @(data_sel)
case (data_sel)
...
How can I synchronize this with the clock?
Hello,
I am using an if else block inside an always @(clock) block. My question is, the if statement is governed by a select and my sensitivity list does not contain this signal as its driven by clock and reset.
Is this a correct representation of the code:
always @(posedge CLK or negedge...
This is how I have written:
parameter input_width = 8;
parameter bit_width = 1; //in this case to shift 1 bit at a time
input [input_width-1:0] input_data;
reg [input_width-1:0] shift_reg;
always @(posedge CLK or negedge RST)
begin
if (!RST) shift_reg <= input_data;
else shift_reg...
It does work because I can see it in my simulation. It just takes the previous appended value and appends more 0's to it. I need to do it this way because I cannot add the 'load' signal. I cant have additional inputs so I just load the data on reset itself.
Hello,
Thank you so much for your help. I will keep that in mind. I am new to Verilog so this really helped.
Another small issue I am facing is that I want my "Shifter" to be variable width; as in the number of 0's being appended to shift_reg is variable (parameterized) .
Like
shift_reg =...
I need to use each bit of the input_data in an incrementing manner in every clock cycle.
So in 1st clock, I want to make use of input_data[0]
in 2nd clock cycle, I want to use input_data[1] ... and so on.
The code I have written seems to work by taking the next bit in each clock. Does it seem...
Why?
I tried doing this
always@(posedge clock) begin
if (reset) shift_reg = input_data;
else shift_reg = {1'b0, input_data[7:1]};
So all of the data gets loaded in in the first cycle after reset .
This way its achieved in one cycle. Either way I want to use the last bit so I just...
Shift register implementation without load signal
I want to implement the shift register without the load signal
This is the original code
always @(posedge clock) begin
if (reset) shift_data = 0;
else if (load) shift_data = input_data;
else shift_data = {1'b0, shift_data[7:1]}...
I desire to implement an operation which uses shifting of data and using the MSB for output side.
One data needs to be shifted 1 bit at a time and the MSB of this shifted data needs to be used in every cycle with another input data.
I am having an issue with the fact that the MSB bit isnt...
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