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balance cts for generated clocks
While in the clk tree root, generate several clk signals in several delay step,
routing pre-delay clk to gated (or generated clk) signal
I have checked the library the cell DFZRBCHD
,the hold time did have negative value. What's the meaning of this?
TKS
Added after 55 minutes:
I got it, most of the FF's hold time are negative,
To aoid the clk skew effect.
The data and clk phase in the FF can be adjusted to make the
outside...
Shouldn't setup time be checked before clk sampling edge so use "-"
Shouldn't holdtime be checked after clk edge so use "+" hold time,
Why you said using "-" is correct?
Mainly because of the notoriously inaccuracte of wireload model, adding
buffer in dc may doesn't make sense.However, if you wanna run presim
with timing , you canot do it with hold time violation.
I got the min path analysis here & I doubt the analysis
Poin Incr path
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clock clk(rising edge)...
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