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Recent content by roger

  1. roger

    How do you balance Generated clock?

    balance cts for generated clocks While in the clk tree root, generate several clk signals in several delay step, routing pre-delay clk to gated (or generated clk) signal
  2. roger

    How to define max_fanout max_transition max_capacitance ?

    max fanout limit 1. 4(3) means 12? 2. max_capacitance < 4 unit cell area, sounds so strange? can you explain it more detailly? TKS
  3. roger

    How to define max_fanout max_transition max_capacitance ?

    max_capacitance I mean set these constraints
  4. roger

    How to define max_fanout max_transition max_capacitance ?

    max_transition Dear: How to define max_fanout/max_transition/max_capacitance in the design, please give me some advice or experience. B.R
  5. roger

    how to dump all signal waveform when import VHDL int Verilog

    vcdpluson in vhdl avoid using variables in your VHDL design. VCD file seemed cannot record them
  6. roger

    Looking for nc-verilog commands

    +sdf_cmd_file+ 2 Product Version 3.2 1 Overview of the Cadence® NC-Verilog® Simulator . . . . . . . . . . . . . . . . . . . . . . . . . 23 Native Compiled Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 The Interleaved Native...
  7. roger

    create_generated_clock problem?

    create_generated_clock command I guess you forgot to describe the source clk pin. DC don't know it, so the create_generated_clock fail
  8. roger

    can any explain the hold time for me?

    I have checked the library the cell DFZRBCHD ,the hold time did have negative value. What's the meaning of this? TKS Added after 55 minutes: I got it, most of the FF's hold time are negative, To aoid the clk skew effect. The data and clk phase in the FF can be adjusted to make the outside...
  9. roger

    can any explain the hold time for me?

    Shouldn't setup time be checked before clk sampling edge so use "-" Shouldn't holdtime be checked after clk edge so use "+" hold time, Why you said using "-" is correct?
  10. roger

    set_fix_hold ,what means?

    Mainly because of the notoriously inaccuracte of wireload model, adding buffer in dc may doesn't make sense.However, if you wanna run presim with timing , you canot do it with hold time violation.
  11. roger

    can any explain the hold time for me?

    I got the min path analysis here & I doubt the analysis Poin Incr path ---------------------------------------------------------------------------------- clock clk(rising edge)...
  12. roger

    how to avoid back slash "\" in dc

    as title how to avoid back slash "\" in dc tks
  13. roger

    False Paths and Multi Cycle Paths

    false path: Normal signals flow never pass through . multicycle path: timing path that costs several clk cycles .
  14. roger

    Core limited and Pad limited design

    PAD limited is good for test chip, you can hace lots of pin to strobe inside the chip, Core limited is good for economical , you won't waste your die.
  15. roger

    The function of a lock-up latch

    lockup latch see material on this page

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