Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The last hours I tried to decipher the above brain teaser. In my netlist I have the subcircuit shown below together with other subcircuits:
Q1 Vbe1 Vbe1 GND GND npnVS M=8
Q2 Vbe2 Vbe2 GND GND npnVS M=2
Q3 Vbe3 Vbe3 GND GND npnVS M=1
*R1 Vctrl Vbe1 78.0k TC1=-0.000105
*M1 Vctrl Vctrl...
I simulate a clock oscillator with hspice using a priopretary MOSFET model (.option scale=0.12u) . The weird thing is that in Hspice X-2005.09 under Windows 7 there is no problem at all.
However, when I try to simulate the exactly same netlist in Hspice A-2008.03-SP1 under Linux I get...